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MOV Rd,Cd is MR encoded but the control register is operand 2
not operand 1 hence this needs to be MODRM_REG not MODRM_RM.
While MOV Cd,Rd is RM encoded registers are also swapped, so
it also needs to be MODRM_REG as well (as it already correctly is).
This fixes incorrect UD2 reportings leading to invalid traps
reported in O3 on X86 FS introduced with 4e939a7 .
Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8
Reviewed-on: https://gem5-review.googlesource.com/4861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Make the traceData panic for Vectors a warn_once. It's a pity it's
not implemented but it's not a reason to abort the simulation entirely.
Change-Id: I5e97258fd4e3fa385cfe0c4b400524d1f7b154df
Reviewed-on: https://gem5-review.googlesource.com/4860
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The primary difference between loadState and unserialize, at least when
eventually using the default SimObject implementation of loadState, is that
unserialize is called only if there's a corresponding section in the
checkpoint being restored. In this particular case, the AlphaProcess class
calls the generic Process unserialize function, and that does other critical
initialization like set up the processes page table. If the unserialize
function isn't called, other serious problems would break the simulation
anyway.
This removes the final custom implementation of loadState.
Change-Id: If50062392196bd37efd5ba04fd7aee6907b00dc6
Reviewed-on: https://gem5-review.googlesource.com/4741
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The MuxingKvmGic class defined a few functions related to checkpointing which
did nothing other than call the underlying Pl390 implementation. These are
unnecessary in general, and are particularly unnecessary for the loadState
function which is a very lightly used part of the checkpointing interface.
It's not actually defined in Pl390 either, and falls through to the
underlying implementation.
Change-Id: I84aae13d4966df0f4fdd1a72aee0bf1af01392ff
Reviewed-on: https://gem5-review.googlesource.com/4760
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This stat is only incremented by Alpha. Also move the _hwrei into the Alpha
stats object since it's the class that actually sets up and maintains that
value and it probably should have been there all along.
Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0
Reviewed-on: https://gem5-review.googlesource.com/4601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The kernel stat mechanism should really be refactored and moved somewhere
else, but in the mean time there's some old cruft that can be cleared away.
Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86
Reviewed-on: https://gem5-review.googlesource.com/4600
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).
Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4284
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4283
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Recent gcc versions complain about a missing VecDisabled not having an
explicit FaultVals instantiation.
Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4282
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4281
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The condition is whether the control register index is valid.
Change-Id: I8a225fcfd4955032b5bbf7d3392ee5bcc7d6bc64
Reviewed-on: https://gem5-review.googlesource.com/4581
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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A condition can be specified which will tell the decoder whether to return
the instruction being requested, or, if the condition fails, UD2.
Change-Id: I0f1c075deb10754ce1dd88be1726a196294e41fd
Reviewed-on: https://gem5-review.googlesource.com/4580
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4263
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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ISA devices typically run in the device event queue. Previously, we
assumed that devices would perform their own EQ migrations as
needed. This isn't ideal since it means we have different conventions
for IO devices and ISA devices. Switch to doing migrations in the KVM
CPU instead to make the behavior consistent.
Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4288
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Old ARM systems used to pass the machine type in the ATAGS list passed
to the kernel. This has been largely deprecated by the introduction of
device trees. Switch to the DTOnly machine type by default in gem5
since all new platforms and kernel will require this behavior.
Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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This fixes the function call to clone in syscall_emul.hh where
the x86 version should be called before the base implementation
of clone.
Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3902
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3980
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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To make it clearer what the register indices are for the semantically
meaningful registers defined by src/arch/riscv/registers.hh, the
constants that were defined using other constants were changed to use
the literal values of those constants. This also removes the need to
use the M5_VAR_USED attribute.
Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61
Reviewed-on: https://gem5-review.googlesource.com/4080
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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When both the C and C++ versions are visible, the compiler will complain that
it doesn't know which one to use. By specifying the std namespace, it will
know to use the C++ version.
Change-Id: Ie1bbe1d95eadbad9644b4915c21f924d7d5c0b22
Reviewed-on: https://gem5-review.googlesource.com/4060
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen. The rest of these
assertions will be changed in a later patch.
[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]
Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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Three of the constants defined in arch/riscv/registers.hh
(ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause
the compiler to warn that they are unused, which results in an error.
This patch adds M5_VAR_USED attributes to them to stop this.
Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457
Reviewed-on: https://gem5-review.googlesource.com/4040
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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The LDM instruction that loads to the PC causes a branch to the
instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes.
The interswitch is broken prior to this commit, with LDM to the PC
ignoring the switch.
Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05
Reviewed-on: https://gem5-review.googlesource.com/3520
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I09570e569efe55f5502bc201e03456738999e714
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3920
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C. Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).
[Update diassembly generation for new RegId type.]
[Rebase onto master.]
Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.
[Fix class UImmOp to have an "imm" member rather than "uimm".]
[Update disassembly generation for new RegId class.]
Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
Reviewed-on: https://gem5-review.googlesource.com/3800
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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ARMv8.1 added a second architected event range, 0x4000-0x4040. Events
in this range are discovered using the high word of PMCEID{0,1}_EL0
Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3960
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If an interrupt was pending according to Kvm state during a drain,
the Pl390 model would create an interrupt event that could not be
serviced, preventing the system from draining. The proper behavior
is for the Pl390 not actively being used for simulation to just skip
the GIC state machine that delivers interrupts.
Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3661
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The BaseArmKvmCPU is responsible for forwarding the IRQ and FIQ
signals from gem5's simulated GIC to KVM. However, these signals
shouldn't be used when the in-kernel GIC emulator is used.
Instead of delivering the interrupts to the guest, we should just
ignore them since any such pending interrupts are likely to be an
artifact of CPU switching or incorrect draining.
Change-Id: I083b72639384272157f92f44a6606bdf0be7413c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3660
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Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.
Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.
Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.
This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.
This requires implementing the vector register file for the different
models using the VecRegContainer class.
This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.
The changes also affect how the remote_gdb connection works.
There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.
Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.
Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705
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This commit adds a new generic vector register to have a cleaner
implementation of SIMD ISAs.
Nathanael's idea, Rekai's implementation.
Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2704
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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With the hierarchical RegId there are a lot of functions that are
redundant now.
The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.
Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702
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Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
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The ARM MiscRegs implementation has two interfaces: 'normal'
and 'no effect'. The latter acts as a way to access the
backing store without architectural 'effects'. For instance,
a normal write to a timer compare value would call into the
timer model to emulate the device. The 'no effect' interface,
however, would just write the value into the register backing
store and do nothing else.
For Kvm execution, a delicate balance must be struck for the
timer device specifically. We need the code in the model
to be run, because it contains state other than the register
backing store that must stay in sync. On the other hand, we
don't necessarily want the timer model to schedule gem5
events when this happens.
In this commit, we ensure that we use the 'effectful'
MiscReg interface when copying the CP15 timer registers
from Kvm back into gem5. The prior commit makes sure
that this doesn't generate unnecessary timer events
or interrupts.
Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9
Reviewed-on: https://gem5-review.googlesource.com/3543
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The check was nearly completely generic anyway,
with the exception of the Kvm CPU type.
This will make it easier for other parts of the
codebase to do similar checks.
Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da
Reviewed-on: https://gem5-review.googlesource.com/3540
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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32bit and 64bit Linux have different arguments passed to the
__switch_to() function that gem5 hooks into in order to collect context
switch statistics. 64bit Linux provides the task_struct pointer to the
next task that will be switched to, which means we don't have to look
up the task_struct from thread_info as we do in 32bit ARM Linux.
This patch adds a second set of accessors to ThreadInfo to extract
details such as the pid, tgid, task name, etc., directly from a
task_struct. The existing accessors maintain their existing behavior by
first looking up the task_struct and then calling these new accessors.
A 64-bit variant of the DumpStatsPCEvent class is added that uses these
new accessors to get the task details for the context switch dumps
directly from the task_struct passed to __switch_to().
Change-Id: I63c4b3e1ad64446751a91f6340901d5180d7382d
Reviewed-on: https://gem5-review.googlesource.com/2640
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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Change-Id: I08de5f72513645d1fe92bde99fa205dde897e951
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3747
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I912601b6f781a0bbedd06583c059589374f6d5c6
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3720
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <joe.gross@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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GDB breaks if more bytes are sent than the transmitted registers
actually need. Therefore the GdbRegCache struct needs to be packed to
prevent padding at the end.
Change-Id: Ib2c14eb70becdac609eb4f475d5dddbd5bcc60da
Signed-off-by: Matthias Hille <matthiashille8@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/3020
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Remove redundant information from the ExtMachInst, hash the vex
information to ensure the decode cache works properly, print the vex info
when printing an ExtMachInst, consider the vex info when comparing two
ExtMachInsts, fold the info from the vex prefixes into existing settings,
remove redundant decode code, handle vex prefixes one byte at a time and
don't bother building up the entire prefix, and let instructions that care
about vex use it in their implementation, instead of developing an entire
parallel decode tree.
This also eliminates the error prone vex immediate decode table which was
incomplete and would result in an out of bounds access for incorrectly
encoded instructions or when the CPU was mispeculating, as it was (as far
as I can tell) redundant with the tables that already existed for two and
three byte opcodes. There were differences, but I think those may have
been mistakes based on the documentation I found.
Also, in 32 bit mode, the VEX prefixes might actually be LDS or LES
instructions which are still legal in that mode. A valid VEX prefix would
look like an LDS/LES with an otherwise invalid modrm encoding, so use that
as a signal to abort processing the VEX and turn the instruction into an
LES/LDS as appropriate.
Change-Id: Icb367eaaa35590692df1c98862f315da4c139f5c
Reviewed-on: https://gem5-review.googlesource.com/3501
Reviewed-by: Joe Gross <joe.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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When the LiveProcess class was renamed to be just Process, the CL author
also changed the syscall function from a virtual function into a regular
one. Unfortunately, the I386Process class overrode the syscall function
to adjust the return address so that control would return to the right
place. Without that adjustment, 32 bit x86 process would segfault and die
immediately after their first system call.
This change reinstates the virtual specifier on the base syscall function,
and adds an override keyword on the I386Process's version so that it won't
be orphaned again in the future. It also fixes some small style issues the
style checker script complained about.
Change-Id: I0d1178ea0eda6676050c8fc043820a2bb4d99c0d
Reviewed-on: https://gem5-review.googlesource.com/3500
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The PMU model currently doesn't calculate the PMU event counter index
correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this
obvious mistake.
Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3121
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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This patch fixes a problem with RISC-V initial stack setup in SE mode
where the AT_RANDOM aux vector value contains an address that is too
close to the top of the stack and doesn't fit the required 16 bytes. To
fix this, the program header table was added to the top of the stack
just like the RISC-V proxy kernel does.
Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3
Reviewed-on: https://gem5-review.googlesource.com/3401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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The ISA code for ARM calculates min and max elements for types using
bit manipulation. That triggers some warnings, treated as errors, as
the compiler can tell that there is an overflow and the sign
flips. Fixed using standard lib definitions instead.
Change-Id: Ie2331b410c7f76d4bd87da5afe9edf20c8ac91b3
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Compiling gem5 with recent version of clang (4 and 5) triggers
warnings that are treated as errors:
* Global templatized static functions result in a warning if they
are not used. These should either be declared as static inline or
without the static identifier to avoid the warning.
* Some templatized classes contain static variables. The
instantiated versions of these variables / templates need to be
explicitly declared to avoid a compiler warning.
Change-Id: Ie8261144836e94ebab7ea04ccccb90927672c257
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3420
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The new version modularizes the implementation of the various commands,
gets rid of dynamic allocation of the register cache, fixes some small
style problems, and uses exceptions to simplify error handling internal to
the GDB stub.
Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2
Reviewed-on: https://gem5-review.googlesource.com/3280
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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If the operands were 64 bit, an intermediate calculation could lose a
carry bit. This change rearranges that intermediate calculation if the
operand width is large, and reworks the microop implementation in general
in an attempt to make it easier to understand.
Change-Id: Ib36333f3f2695a33cd9623e43682de22ebd2e7ea
Reviewed-on: https://gem5-review.googlesource.com/3381
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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