summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Expand)Author
2011-09-19MIPS: Add constructors to the fault classes.Gabe Black
2011-09-19MIPS: Use the CRTP to streamline the Fault class definitions.Gabe Black
2011-09-19SPARC: Remove #if FULL_SYSTEMs from the ISA description.Gabe Black
2011-09-19MIPS: Get rid of #if style config checks in the ISA description.Gabe Black
2011-09-19MIPS: Guard SystemCallFault::invoke consistently.Gabe Black
2011-09-19MIPS: Get rid of the unused (and partially defined) CacheError fault.Gabe Black
2011-09-19Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.Gabe Black
2011-09-19X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.Gabe Black
2011-09-19PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.Gabe Black
2011-09-18Pseudoinst: Add an initParam pseudo inst function.Gabe Black
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-09-13LSQ: Only trigger a memory violation with a load/load if the value changes.Ali Saidi
2011-09-10MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.Deyuan Guo
2011-09-09StaticInst: Merge StaticInst and StaticInstBase.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-09-09Stack: Tidy up some comments, a warning, and make stack extension consistent.Gabe Black
2011-09-08ISA parser: Don't look for operands in strings.Gabe Black
2011-09-08ISA parser: Match /* */ and // style comments.Gabe Black
2011-09-05X86: Make sure instruction flags are set properly even on 32 bit machines.Gabe Black
2011-09-05X86,TLB: Make sure the "delayedResponse" variable is always set.Gabe Black
2011-09-02TLB: comments and a helpful warning.Lisa Hsu
2011-08-19ARM: Mark some variables uncacheable until boot all CPUs are enabled.Ali Saidi
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-08-19ARM: Add support for Versatile Express boardsAli Saidi
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
2011-08-19ARM: Fix a memory leak with the table walker.Ali Saidi
2011-08-13X86: Use IsSquashAfter if an instruction could affect fetch translation.Gabe Black
2011-07-15ARM: Fix SWP/SWPB undefined instruction behaviorWade Walker
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
2011-07-11X86: implements copyRegs() functionNilay Vaish
2011-07-11ISA: Get rid of the unused mem_acc_type template parameter.Gabe Black
2011-07-07alpha:hwrei:rollback for o3Korey Sewell
2011-07-05grammar: better encapsulation of a grammar and parsingNathan Binkert
2011-07-05ISAs: Streamline some spots where Mem is used in the ISA descriptions.Gabe Black
2011-07-05ISA parser: Define operand types with a ctype directly.Gabe Black
2011-07-05ISA parser: Simplify operand type handling.Gabe Black
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
2011-07-02ISA: Use readBytes/writeBytes for all instruction level memory operations.Gabe Black
2011-07-02X86: Fix store microops so they don't drop faults in timing mode.Gabe Black
2011-06-28arch: print next upc correctlyNilay Vaish
2011-06-22mips: fix nmsub and nmadd definitionsDeyaun Guo
2011-06-21X86: Eliminate an unused argument for building store microops.Gabe Black
2011-06-19mips: mark unaligned access flag as trueKorey Sewell
2011-06-19inorder/dtb: make sure DTB translate correct addressKorey Sewell
2011-06-19alpha: fix warn_once for prefetchesKorey Sewell
2011-06-19alpha: naming for dtb faultsKorey Sewell
2011-06-19alpha: make hwrei a control instKorey Sewell