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AgeCommit message (Expand)Author
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
2017-10-31x86: Fix VEX instruction decoding.Gabe Black
2017-10-20arch-arm: RBIT instruction using mirroring funcGiacomo Travaglini
2017-10-17scons: Stop generating inc.d in the isa parser.Gabe Black
2017-10-17arch-arm: Fix inverted 32/64-bit check in GDBBoris Shingarov
2017-10-13arch-arm: Signal an event when executing store exclusivesNikos Nikoleris
2017-10-13mem: Signal the local monitor when clearing the global monitorNikos Nikoleris
2017-09-27arch-x86: fix CondInst decoding for MOV to Control RegistersBjoern A. Zeeb
2017-09-27arch: change panic for Vector traceData to warn_onceBjoern A. Zeeb
2017-09-21alpha: Move some initialization logic from loadState into unserialize.Gabe Black
2017-09-20kvm: arm: Get rid of functions which just wrap the subclasses version.Gabe Black
2017-09-11stats: Move the swpipl function into the Alpha kernel stats.Gabe Black
2017-09-11stats: Get rid of some kernel stats related cruft.Gabe Black
2017-08-30arch-arm: Only increment SW PMU counters on writes to PMSWINCJose Marinho
2017-08-30arch-arm: Add missing override keywords in fault.hhAndreas Sandberg
2017-08-30arch-x86: Add missing override in the X86 TLBAndreas Sandberg
2017-08-30arch-sparc: Add a FaultVals instantiation for VecDisabledAndreas Sandberg
2017-08-30arch-alpha: Add missing overridesAndreas Sandberg
2017-08-28x86: Use the new CondInst format for moves to/from control registers.Gabe Black
2017-08-28x86: Add a "CondInst" format for conditionally decoded instructions.Gabe Black
2017-08-01arch-arm: Use named constants for m5op instructionsAndreas Sandberg
2017-08-01kvm, arm: Switch to the device EQ when accessing ISA devicesAndreas Sandberg
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
2017-07-17x86: Add stats to X86 TLBSwapnil Haria
2017-07-17riscv: Define register index constants using literalsAlec Roelke
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
2017-07-13arch-arm: fix ldm of pc interswitching branchGedare Bloom
2017-07-12mips, x86: Refactor some Event subclasses into lambdasSean Wilson
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
2017-07-10arch-arm: Support PMU evens in the 0x4000-0x4040 rangeJose Marinho
2017-07-07kvm, arm: don't create interrupt events while saving GIC stateCurtis Dunham
2017-07-07kvm, arm: Don't forward IRQ/FIQ when using the kernel's GICAndreas Sandberg
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05arch: added generic vector registerRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2017-07-05arm,kvm: update CP15 timer model when exiting KvmCurtis Dunham
2017-07-05kvm: move Kvm check from ARM Kvm GIC to SystemCurtis Dunham
2017-06-22arm,sim: fix context switch stats dumps for ARM64/LinuxPaul Rosenfeld
2017-06-20sim, x86: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-06-20arm: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-06-15x86: Add consistent overrides to process.hhSean Wilson
2017-06-15x86: Fixed remote debugging of simulated codeMatthias Hille
2017-05-26x86: Rework how VEX prefixes are decoded.Gabe Black
2017-05-25x86: sim: Make 32 bit x86 processes work again.Gabe Black