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2006-12-17Convert Alpha (and finish converting MIPS) to newSteve Reinhardt
InstObjParam interface. src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/fp.isa: src/arch/alpha/isa/int.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/isa/mem.isa: src/arch/alpha/isa/pal.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/util.isa: Get rid of CodeBlock calls to adapt to new InstObjParam interface. src/arch/isa_parser.py: Check template code for operands (in addition to snippets). src/cpu/o3/alpha/dyn_inst.hh: Add (read|write)MiscRegOperand calls to Alpha DynInst. --HG-- extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-17Started removing "CodeBlock" objects from the mips isa description.Gabe Black
--HG-- extra : convert_revision : 2e174ecfce8c86732e1addfc23e961429b86a570
2006-12-17Compilation fix after messy merge.Gabe Black
--HG-- extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472
2006-12-16Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/isa_parser.py: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/cpu/o3/iew_impl.hh: Hand Merge --HG-- extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
2006-12-16Made changes to CWP be non speculative.Gabe Black
--HG-- extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
2006-12-16Changes to the isa_parser and affected files to fix an indexing problem with ↵Gabe Black
split execute instructions and miscregs aliasing with integer registers. src/arch/isa_parser.py: Rearranged things so that classes with more than one execute function treat operands properly. 1. Eliminated the CodeBlock class 2. Created a SubOperandList 3. Redefined how InstObjParams is constructed To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions. Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays. src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/branch.isa: src/arch/sparc/isa/formats/integerop.isa: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa/formats/nop.isa: src/arch/sparc/isa/formats/priv.isa: src/arch/sparc/isa/formats/trap.isa: Rearranged to work with new InstObjParam scheme. src/cpu/o3/sparc/dyn_inst.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays. src/cpu/simple/base.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. --HG-- extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-15Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
2006-12-15some small general fixes to make everythign work nicely with other ISAs, now ↵Lisa Hsu
we can merge back with newmem. exetrace.cc: wrap this variable between FULL_SYSTEM #ifs mmaped_ipr.hh: fix for build miscregfile.cc: fixes for HPSTATE access during SE mode src/arch/sparc/miscregfile.cc: fixes for HPSTATE access during SE mode src/arch/mips/mmaped_ipr.hh: fix for build src/cpu/exetrace.cc: wrap this variable between FULL_SYSTEM #ifs --HG-- extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
2006-12-15tlb.cc:Lisa Hsu
fix namespace indentations src/arch/alpha/tlb.cc: fix namespace indentations --HG-- extra : convert_revision : 327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
2006-12-15Optimized the TLB translations with some cachingAli Saidi
--HG-- extra : convert_revision : f79f863393f918ff9363b2c261f8c0dfec64312e
2006-12-14flesh out twinx asisAli Saidi
fix TICK register reads reduce the number of readmiscreg accesses, implement tsb pointer stuff src/arch/sparc/asi.cc: flesh out twinx asis src/arch/sparc/miscregfile.cc: fix TICK register reads src/arch/sparc/tlb.cc: reduce the number of readmiscreg accesses, implement tsb pointer stuff --HG-- extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
2006-12-13fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.Lisa Hsu
--HG-- extra : convert_revision : 4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
2006-12-12Merge zizzer:/bk/newmem/Gabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
2006-12-12Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)Ali Saidi
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing) Fix tcc instruction igoner in legion-lock stuff to be correct in all cases Have console interrupts warn rather than panicing until we figure out what to do with interrupts src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add a magic miscreg which reads all the bits the tlb needs in one go src/arch/sparc/tlb.cc: initialized the context type and id to reasonable values and handle block init stores src/arch/sparc/tlb_map.hh: fix bug in tlb map code src/base/range_map.hh: fix bug in rangemap code and add range_multimap (these are probably useful for bus range stuff) src/cpu/exetrace.cc: fixup tcc ignore code to be correct src/dev/sparc/t1000.cc: make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out src/unittest/rangemaptest.cc: fix up the rangemap unit test to catch the missing case --HG-- extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
2006-12-12Rename the StaticInst-based (read|set)(Int|Float)Reg methods to ↵Steve Reinhardt
(read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. --HG-- extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
2006-12-09fix lisa's hand mergeAli Saidi
--HG-- extra : convert_revision : d25604156ae0b2cf29d92fb960b8f5d77427985b
2006-12-09Merge zizzer:/bk/sparcfsAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : c51fd95f7acd7cffb3ea705d7216772f0a801844
2006-12-09Allocate the correct number of global registersAli Saidi
Fix fault formating and code for traps fix a couple of bugs in the decoder Cleanup/fix page table entry code Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data src/arch/sparc/faults.cc: Fix fault formating and code for traps src/arch/sparc/intregfile.hh: allocate the correct number of global registers src/arch/sparc/isa/decoder.isa: fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate src/arch/sparc/pagetable.hh: cleanup/fix page table code src/arch/sparc/tlb.cc: implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents src/arch/sparc/tlb.hh: add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging src/cpu/exetrace.cc: dump tlb entries on error, don't consider differences the cycle we take a trap to be bad. --HG-- extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
2006-12-08Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 src/arch/sparc/ua2005.cc: hand merge --HG-- extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
2006-12-08mostly implemented SOFTINT relevant interrupt stuff.Lisa Hsu
src/arch/sparc/interrupts.hh: add in thread_context.hh to get access to tc. get rid of stubs that don't make sense right now. implement checking and get softint interrupts src/arch/sparc/miscregfile.cc: softint should be OR-ed on a write. src/arch/sparc/miscregfile.hh: add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs. src/arch/sparc/ua2005.cc: implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write. --HG-- extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
2006-12-07get legion/m5 to first tlb miss faultAli Saidi
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices --HG-- extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-07Make branches handle the lack of a symbol table or the lack of a symbol ↵Gabe Black
gracefully. --HG-- extra : convert_revision : 7bb16405999b86f9fa082a6d44da43d346edc182
2006-12-07Change how Page Faults work in SPARC. It now prints the faulting address, ↵Gabe Black
and panics instead of fatals. This isn't technically what it should do, but it makes gdb stop at the panic rather than letting m5 exit. --HG-- extra : convert_revision : 3b14c99edaf649e0809977c9579afb2b7b0d72e9
2006-12-06Handle access to ASI_QUEUEAli Saidi
Add function for interrupt ASIs add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: Add function for interrupt ASIs src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: Add QUEUE asi/misc registers src/arch/sparc/regfile.cc: add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/tlb.cc: Handle access to ASI_QUEUE --HG-- extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
2006-12-06Many more fixes for SPARC_FS. Gets us to the point where SOFTINT startsAli Saidi
getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-06Made the alpha setSyscallReturn take a ThreadContext pointer instead of a ↵Gabe Black
RegFile *. --HG-- extra : convert_revision : 021a1fe6760df1daf6299d46060371a5310f008a
2006-12-06Added a flattenIntIndex function for Alpha.Gabe Black
--HG-- extra : convert_revision : 5ed79ed18e443118a28d6890327c55a6a3fcd325
2006-12-06Change to use -return_value.value like other implementations.Gabe Black
--HG-- extra : convert_revision : 513422c1c8c24f3662e6a423d13ee033424aa44b
2006-12-06Some changes for misc regs which were changed into unofficial integer ↵Gabe Black
registers, and moved the flattenIndex function into the register file. --HG-- extra : convert_revision : 6b797c793a6c12c61a23f0f78a1ea1c88609553e
2006-12-06Reorganize the includes and add an include for misc.hh.Gabe Black
--HG-- extra : convert_revision : 484b2d07a1e8b3879c35d80bf16b73fd0cc9be1f
2006-12-06Added some debug output, and made sure not to accidentally ask for the ↵Gabe Black
result of a store conditional. --HG-- extra : convert_revision : d36ff9e2343fdf78a3bc16a1348975fdba5c55e2
2006-12-06Some basic fix ups, and CWP is no longer set explicitly.Gabe Black
--HG-- extra : convert_revision : 1dde5594a2bcfd9fb5ad974360b3dc035f1624e5
2006-12-06Changed the integer register file to work with flattened indices.Gabe Black
--HG-- extra : convert_revision : c5153c3c712e5d18b5233e1fd205806adcb30654
2006-12-06Change MIPS's setSyscallReturn to use a thread context.Gabe Black
--HG-- extra : convert_revision : 618f8404ec5380615e28170d761b2fcdf9c07d96
2006-12-06Added basic flatten function for mips.Gabe Black
--HG-- extra : convert_revision : 2c32851584001734d139f36c4d58c5e61067fcfc
2006-12-05Move the SyscallReturn class into sim/syscallreturn.hh. Also move some ↵Gabe Black
miscregs into the integer register file so they get renamed. src/arch/alpha/syscallreturn.hh: src/arch/mips/syscallreturn.hh: src/sim/syscallreturn.hh: Move the SyscallReturn class into sim/syscallreturn.hh src/arch/sparc/faults.cc: src/arch/sparc/isa/operands.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/arch/sparc/process.cc: src/arch/sparc/sparc_traits.hh: Move some miscregs into the integer register file so they get renamed. --HG-- extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
2006-12-04forgot to commit miscreg fileAli Saidi
--HG-- extra : convert_revision : c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
2006-12-04Merge zizzer:/bk/sparcfsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmemmid --HG-- extra : convert_revision : 45d9599dd883e10c283812c1c241c20323f44cec
2006-12-04Add in code to pass the ASI to translation.Gabe Black
--HG-- extra : convert_revision : 4a985635cda7680abcddaf0bc9579fa03d5bc7c6
2006-12-04reogranize code to split off FS only misc regs with effect into their own ↵Ali Saidi
file (reducing the number of if FULL_SYSTEM defines and includes) Protect other pieces of code so that sparc compiles SE again src/arch/sparc/SConscript: Add ua2005.cc back into SConscript src/arch/sparc/miscregfile.hh: add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness src/arch/sparc/mmaped_ipr.hh: wrap handleIpr* with if full_system so it compiles under se src/arch/sparc/ua2005.cc: reorganize edit fs only miscreg functions src/cpu/exetrace.cc: protect legion code so it doesn't try to compile under se --HG-- extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
configs/common/FSConfig.py: seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config. src/arch/sparc/isa/decoder.isa: change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect src/arch/sparc/miscregfile.cc: For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this). Use instruction count from cpu rather than cycles because that is what legion does we can change it back after were done with legion src/base/bitfield.hh: add a new function mbits() that just masks off bits of interest but doesn't shift src/cpu/base.cc: src/cpu/base.hh: add instruction count to cpu src/cpu/exetrace.cc: src/cpu/m5legion_interface.h: compare instruction count between legion and m5 too src/cpu/simple/atomic.cc: change asserts of packet success to if panics wrapped with NDEBUG defines so we can get some more useful information when we have a bad address src/dev/isa_fake.cc: src/dev/isa_fake.hh: src/python/m5/objects/Device.py: expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses src/python/m5/objects/System.py: convert some tabs to spaces src/python/m5/objects/T1000.py: add more fake devices for each l1 bank and each memory controller --HG-- extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
2006-11-30Load the hypervisor symbols twice, once with an address mask so that we can ↵Ali Saidi
get symbols for where it's copied to in memory Add the ability to use an address mask for symbol loading Rather then silently failing on platform accesses panic Move BadAddr/IsaFake no Device from Tsunami Let the system kernel be none, but warn about it configs/common/FSConfig.py: We don't have a kernel for sparc yet src/arch/sparc/system.cc: Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory src/base/loader/aout_object.cc: src/base/loader/aout_object.hh: src/base/loader/ecoff_object.cc: src/base/loader/ecoff_object.hh: src/base/loader/elf_object.cc: src/base/loader/elf_object.hh: src/base/loader/object_file.hh: src/base/loader/raw_object.cc: src/base/loader/raw_object.hh: Add the ability to use an address mask for symbol loading src/dev/sparc/t1000.cc: Rather then silently failing on platform accesses panic src/dev/sparc/t1000.hh: fix up a couple of platform comments src/python/m5/objects/Bus.py: src/python/m5/objects/Device.py: src/python/m5/objects/T1000.py: src/python/m5/objects/Tsunami.py: Move BadAddr/IsaFake no Device from Tsunami src/python/m5/objects/System.py: Let kernel be none src/sim/system.cc: Let the system kernel be none, but warn about it --HG-- extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
2006-11-29Add TLB DprintfsAli Saidi
fix addr alignment problem --HG-- extra : convert_revision : c691611d4d32bc95d0ae30243b30cd6634e7772b
2006-11-29Fixes to get compilation.Gabe Black
--HG-- extra : convert_revision : cd6b496c4e4b32ce2a639eb9a2b6fbd62dfff2d1
2006-11-29Merge zizzer:/bk/sparcfsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmemmid src/arch/sparc/isa_traits.hh: src/arch/sparc/miscregfile.hh: hand merge --HG-- extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
2006-11-29Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : c358d5e3211756bbf905eef2a62b65a2e56a86f3
2006-11-29Add support for mmapped iprs to atomic cpuAli Saidi
src/arch/SConscript: add mmaped_ipr.hh to switch headers src/arch/sparc/asi.hh: make ASI_IMPLICT=0 so by default nothing needs to be done src/arch/sparc/miscregfile.hh: miscregfile no longer needs to include asi.hh src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: implement panic instructions for mmaped ipr reads src/cpu/simple/atomic.cc: add check for mmaped iprs and handle them if it exists src/mem/request.hh: allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits --HG-- extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
2006-11-24Initial changes to get O3 working with SPARCGabe Black
src/arch/sparc/process.cc: MachineBytes doesn't exist any more. src/arch/sparc/regfile.cc: Add in the miscRegFile for good measure. src/cpu/o3/isa_specific.hh: Add in a section for SPARC src/cpu/o3/sparc/cpu.cc: src/cpu/o3/sparc/cpu.hh: src/cpu/o3/sparc/cpu_builder.cc: src/cpu/o3/sparc/cpu_impl.hh: src/cpu/o3/sparc/dyn_inst.cc: src/cpu/o3/sparc/dyn_inst.hh: src/cpu/o3/sparc/dyn_inst_impl.hh: src/cpu/o3/sparc/impl.hh: src/cpu/o3/sparc/params.hh: src/cpu/o3/sparc/thread_context.cc: src/cpu/o3/sparc/thread_context.hh: Sparc version of this file. --HG-- extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-24Merge zower:/eecshome/m5/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmemo3 --HG-- extra : convert_revision : e8d6ce19a83fe526112c1dd61c48196eb8c0951f
2006-11-24Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 11:27:17 +0000