summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Expand)Author
2011-01-07scons: show sources and targets when building, and colorize output.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-09ARM: Get rid of some unused FP operands.Gabe Black
2010-12-08Alpha: Take advantage of new PCState syntax.Gabe Black
2010-12-08MIPS: Take advantage of new PCState syntax.Gabe Black
2010-12-08POWER: Take advantage of new PCState syntax.Gabe Black
2010-12-08SPARC: Take advantage of new PCState syntax.Gabe Black
2010-12-08X86: Take advantage of new PCState syntax.Gabe Black
2010-12-07ISA: Get the parser to support pc state components more elegantly.Gabe Black
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-11-23X86: Obey the PCD (cache disable) bit in the page tables.Gabe Black
2010-11-22X86: Mark IO space accesses as uncachable.Gabe Black
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-11-15ARM: Add comment about the organization of the IT state registerAli Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-15SCons: Cleanup SCons output during compileAli Saidi
2010-11-15ARM: Add support for GDB on ARMWilliam Wang
2010-11-15ARM: Make utility.hh meet style guidelinesAli Saidi
2010-11-15ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.Ali Saidi
2010-11-15ARM: Add support for switching CPUsAli Saidi
2010-11-15ARM: Use the correct delete operator for RFEAli Saidi
2010-11-15ARM: Fix SRS instruction to micro-code memory operation and register update.Ali Saidi
2010-11-15ARM: Do something predictable for an UNPREDICTABLE branch.Ali Saidi
2010-11-11SPARC: Clean up some historical style issues.Gabe Black
2010-11-08X86: Fix X86_FS compilation.Gabe Black
2010-11-08ARM: Add some TLB statistics for ARMAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi
2010-11-08ARM: Keep the warnings to a minimum.Ali Saidi
2010-11-08ARM: Don't return the result of a table walk the same cycle it's completed.Ali Saidi
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-11-08ARM: Make all ARM uops delayed commit.Ali Saidi
2010-11-08sim: Use forward declarations for ports.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-29X86: Fault on divide by zero instead of panicing.Gabe Black
2010-10-29X86: Make syscalls also serialize after.Gabe Black
2010-10-22X86: Make nop a regular, non-microcoded instruction.Gabe Black
2010-10-22X86: Implement genMachineCheckFault.Gabe Black
2010-10-22X86: Make syscall instructions non-speculative in SE.Gabe Black
2010-10-22ISA: Simplify various implementations of completeAcc.Gabe Black
2010-10-22ARM: Don't pretend to writeback registers in initiateAcc.Gabe Black
2010-10-16Mem: Reclaim some request flags used by MIPS for alignment checking.Gabe Black
2010-10-15GetArgument: Rework getArgument so that X86_FS compiles again.Gabe Black
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 08:37:06 +0000