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AgeCommit message (Expand)Author
2017-12-21arch-arm: Fix StaticInst encoding() methodGiacomo Travaglini
2017-12-19arch-arm: Instruction size methods in StaticInst classGiacomo Travaglini
2017-12-19arch-arm: Change casting type from reinterpret to staticGiacomo Travaglini
2017-12-14arch-riscv: Define AT_RANDOM properlyAlec Roelke
2017-12-14arch-riscv: Increase maximum stack sizeAlec Roelke
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-12-14x86: Use operand size 4 when it would be 2 for cmpxchg8b.Gabe Black
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
2017-12-13x86: Rework how "split" loads/stores are handled.Gabe Black
2017-12-08arm: Change access permission in TPIDRURO and TPIDRURWGiacomo Travaglini
2017-12-08x86,misc: add additional info on faulting X86 instruction, fetched PCMatt Sinclair
2017-12-07arch-riscv: Move compressed ops out of ISAAlec Roelke
2017-12-06x86: Split apart x87's FSW and TOP, and add a missing break.Gabe Black
2017-12-05x86: LOOP's operand size defaults to 64 bits in 64 bit mode.Gabe Black
2017-12-05arm: Add support for the dc {civac, cvac, cvau, ivac} instrNikos Nikoleris
2017-12-05arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructionsNikos Nikoleris
2017-12-05arm: Add CMO support for Non-Cacheable memoryNikos Nikoleris
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-12-01arm: Enable ns registers access in secure modeGiacomo Travaglini
2017-11-30arch-riscv: use sext rather than manual masksAlec Roelke
2017-11-30arch-riscv: Remove spaces around ea_codeAlec Roelke
2017-11-29arch-riscv: Add missing license paragraphsAlec Roelke
2017-11-29arch-riscv: Remove static parts of AMOs out of ISAAlec Roelke
2017-11-29arch-riscv: Move parts of mem insts out of ISAAlec Roelke
2017-11-29arch-riscv: Move unknown out of ISA descriptionAlec Roelke
2017-11-29arch-riscv: Move standard ops out of ISAAlec Roelke
2017-11-28arch-arm: Add haveEL pseudocode functionGiacomo Travaglini
2017-11-28arch-arm: Add assertions when extracting an ArmSystem from a TCGiacomo Travaglini
2017-11-28arch-riscv: Move static_inst into a directoryAlec Roelke
2017-11-22arch-arm: Add support for the brk instructionAndreas Sandberg
2017-11-22arch-arm: HVC instruction undefined in secure EL1Giacomo Travaglini
2017-11-22arch-riscv: Add missing system callsAlec Roelke
2017-11-22sparc: Move integer StaticInst base classes out of the ISA desc.Gabe Black
2017-11-22sparc: Move the mem base classes out of the ISA description.Gabe Black
2017-11-22sparc: Move the microop/macroop base classes out of the ISA desc.Gabe Black
2017-11-22sparc: Return debug faults from unimplemented instructions.Gabe Black
2017-11-22sparc: Pull the unimplemented formats out of the ISA description.Gabe Black
2017-11-22sparc: Pull the "Uknown" StaticInst class out of the ISA description.Gabe Black
2017-11-22sparc: Pull most of the Nop format out of the ISA description.Gabe Black
2017-11-22sparc: Pull more StaticInst base classes out of the ISA desc.Gabe Black
2017-11-22sparc: Pull flat static instruction classes out of the ISA.Gabe Black
2017-11-21arch-arm: ArmPMU refactorJose Marinho
2017-11-21arch-arm: Do not increment PMU cycle event in WFI/WFEJose Marinho
2017-11-21arch-arm: Fix MCR/MRC disassembleGiacomo Travaglini
2017-11-21arch-arm: Fix MSR/MRS disassembleGiacomo Travaglini
2017-11-20arch-arm: Ensure counters keep events on checkpoint resumeJose Marinho
2017-11-20sparc: Pull StaticInst base classes out of the ISA description.Gabe Black
2017-11-17sim: Implement load_addr_mask auto-calculationGeoffrey Blake
2017-11-16arch, arm: Print value being ignored on DummyISA writeSean McGoogan