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path: root/src/arch
AgeCommit message (Expand)Author
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
2017-07-17x86: Add stats to X86 TLBSwapnil Haria
2017-07-17riscv: Define register index constants using literalsAlec Roelke
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
2017-07-13arch-arm: fix ldm of pc interswitching branchGedare Bloom
2017-07-12mips, x86: Refactor some Event subclasses into lambdasSean Wilson
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
2017-07-10arch-arm: Support PMU evens in the 0x4000-0x4040 rangeJose Marinho
2017-07-07kvm, arm: don't create interrupt events while saving GIC stateCurtis Dunham
2017-07-07kvm, arm: Don't forward IRQ/FIQ when using the kernel's GICAndreas Sandberg
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05arch: added generic vector registerRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2017-07-05arm,kvm: update CP15 timer model when exiting KvmCurtis Dunham
2017-07-05kvm: move Kvm check from ARM Kvm GIC to SystemCurtis Dunham
2017-06-22arm,sim: fix context switch stats dumps for ARM64/LinuxPaul Rosenfeld
2017-06-20sim, x86: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-06-20arm: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-06-15x86: Add consistent overrides to process.hhSean Wilson
2017-06-15x86: Fixed remote debugging of simulated codeMatthias Hille
2017-05-26x86: Rework how VEX prefixes are decoded.Gabe Black
2017-05-25x86: sim: Make 32 bit x86 processes work again.Gabe Black
2017-05-24arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMUAndreas Sandberg
2017-05-23arch-riscv: Fix bad stack initializationAlec Roelke
2017-05-23arch-arm: Fix some poorly done type max and min in NEONRekai Gonzalez-Alberquilla
2017-05-19base, sim, arch: Fix clang 5.0 warningsAndreas Sandberg
2017-05-18base: Refactor the GDB code.Gabe Black
2017-05-18syscall_emul, riscv: add override keyword to RISCV Process classBrandon Potter
2017-05-16x86: Fix the multiplication microops.Gabe Black
2017-05-12arm: Remove unused DumpStatsPCEventF class in FreeBSD systemAndreas Sandberg
2017-05-10scons: Use the generalized switching headers on the GPU ISA.Gabe Black
2017-05-10scons: arch: Generalize the switching header code.Gabe Black
2017-05-09arm: Add support for memory-mapped m5opsAndreas Sandberg
2017-05-09kvm, arm: Fix incorrect PSTATE syncAndreas Sandberg
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
2017-05-01arch-sparc: Fix wrong indentation causing warnings for gcc 6Nikos Nikoleris
2017-04-18x86: fixed branching() computation for branch uopsSanti Galan
2017-04-11riscv: Fix crashes with large or frequent mmapsAlec Roelke
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
2017-04-05riscv: fix compatibility with Linux toolchainAlec Roelke
2017-04-05riscv: add remote gdb supportAlec Roelke
2017-04-05riscv: fix error on memory op address overflowAlec Roelke
2017-04-05riscv: enable unaligned memory accessesAlec Roelke
2017-04-03arm, kvm: implement GIC state transferCurtis Dunham