| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-05-17 | includes: use base/types.hh not inttypes.h or stdint.h | Nathan Binkert | |
| 2009-05-17 | types: Move stuff for global types into src/base/types.hh | Nathan Binkert | |
| --HG-- rename : src/sim/host.hh => src/base/types.hh | |||
| 2009-05-13 | mips-merge: merge hello world regress for inorder cpu | Korey Sewell | |
| w/latest changes | |||
| 2009-05-12 | gcc: work around a bogus gcc error | Nathan Binkert | |
| 2009-05-13 | inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp | Korey Sewell | |
| Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU | |||
| 2009-05-13 | arch-mips: add regWidth constant to float regfile | Korey Sewell | |
| 2009-05-12 | alpha-isa: add mt.hh so it can compile with inorder | Korey Sewell | |
| 2009-05-12 | inorder-tlb-cunit: merge the TLB as implicit to any memory access | Korey Sewell | |
| TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * * | |||
| 2009-05-12 | inorder-float: Fix storage of FP results | Korey Sewell | |
| inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store | |||
| 2009-05-12 | inorder-mem: skeleton support for prefetch/writehints | Korey Sewell | |
| 2009-05-12 | inorder-unified-tlb: use unified TLB instead of old TLB model | Korey Sewell | |
| 2009-05-12 | inorder/alpha-isa: create eaComp object visible to StaticInst through ISA | Korey Sewell | |
| Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * * | |||
| 2009-05-12 | inorder-bpred: edits to handle non-delay-slot ISAs | Korey Sewell | |
| Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline | |||
| 2009-05-12 | inorder-alpha-port: initial inorder support of ALPHA | Korey Sewell | |
| Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.) | |||
| 2009-05-12 | isa-parser: made a few changes, but not author-worthy | Korey Sewell | |
| 2009-04-26 | X86: Precompute the default and alternate address and operand size and the ↵ | Gabe Black | |
| stack size. | |||
| 2009-04-26 | X86: Split out the internal memory space from the regular translate() and ↵ | Gabe Black | |
| precompute mode. | |||
| 2009-04-26 | X86: Centralize updates to the handy M5 reg. | Gabe Black | |
| 2009-04-26 | X86: Tell the function that sends int messages who to send to instead of ↵ | Gabe Black | |
| figuring it out itself. | |||
| 2009-04-26 | X86: Make the local APICs register themselves with the IO APIC. | Gabe Black | |
| This is a hack so that the IO APIC can figure out information about the local APICs. The local APICs still have no way to find out about each other. Ideally, when the local APICs update state that's relevant to somebody else, they'd send an update to everyone. Without being able to do a broadcast, that would still require knowing who else there is to notify. Other broadcasts are implemented using assumptions that may not always be true. | |||
| 2009-04-26 | X86: Record the initial APIC ID which identifies an APIC in M5. | Gabe Black | |
| The ID as exposed to software can be changed. Tracking those changes in M5 would be cumbersome, especially since there's no guarantee the IDs will remain unique. | |||
| 2009-04-24 | SPARC: Tighten up the clone system call and SPARCs copyRegs. | Gabe Black | |
| 2009-04-23 | X86: Put the StoreCheck flag with the others, and don't collide with other ↵ | Gabe Black | |
| flags. | |||
| 2009-04-21 | arm: include missing file for arm | Nathan Binkert | |
| 2009-04-21 | arm: Unify the ARM tlb. We forgot about this when we did the rest. | Nathan Binkert | |
| This code compiles, but there are no tests still | |||
| 2009-04-21 | syscall: Resolve conflicts between m5threads and Gabe's recent SE changes. | Steve Reinhardt | |
| 2009-04-21 | Commit m5threads package. | Daniel Sanchez | |
| This patch adds limited multithreading support in syscall-emulation mode, by using the clone system call. The clone system call works for Alpha, SPARC and x86, and multithreaded applications run correctly in Alpha and SPARC. | |||
| 2009-04-19 | X86: Fix the functions that manipulate large bit arrays in the local APIC. | Gabe Black | |
| 2009-04-19 | X86: Fix up a copyright. | Gabe Black | |
| 2009-04-19 | X86: Fix how the TLB handles the storecheck flag. | Gabe Black | |
| 2009-04-19 | X86: Recognize and handle the lock legacy prefix. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of XADD. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTR. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of CMPXCHG. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTS. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of DEC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of INC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of NEG. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of NOT. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of XCHG. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of XOR. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of SUB. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of AND. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of SBB. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of ADC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of OR. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of ADD. | Gabe Black | |
| 2009-04-19 | X86: Implement the stul microop. | Gabe Black | |
| This microop does a store and unlocks the requested address. The RISC86 microop ISA doesn't seem to have an equivalent to this, so I'm guessing that the store following an ldstl is automatically unlocking. We don't do it this way for performance reasons since the behavior is the same. | |||
| 2009-04-19 | X86: Implement the ldstl microop. | Gabe Black | |
| This microop does a load, checks that a store would succeed, and locks the requested address. | |||
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