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2012-01-12mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FSDeyuan Guo
2012-01-12mips: Fix decoder of two float-convert instructionsDeyuan Guo
2012-01-12mips: definition of MIPS64_QNAN in registers.hhDeyuan Guo
2012-01-09X86: Add memory fence to I/O instructionsNilay Vaish
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2012-01-05X86 TLB: Move a DPRINTF to its correct placeNilay Vaish
The DPRINTF for doing protection checks appears after the checks have been carried out. It is possible that the function returns while the checks are being carried, in which case the printf is missed out. This patch moves the DPRINTF before the checks. --HG-- extra : rebase_source : 172896057e593022444d882ea93323a5d9f77a89
2011-12-13gcc: fix unused variable warnings from GCC 4.6.1Nathan Binkert
--HG-- extra : rebase_source : f9e22de341493a25ac6106c16ac35c61c128a080
2011-12-01Device: Make changes necessary to support a coherent page walker cache.Mitchell Hayenga
Adds the flag 'recvSnoops' which enables pagewalkers using DmaPorts, to properly configure snoops. --HG-- extra : rebase_source : 64207bef62c3268ddff2236ee4adae873812325f
2011-12-01ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .Ali Saidi
Squashes the subsequent instructions in O3 pipe after the service call, so that they see the effect of the system call when re-executed. This isn't really an issue with FS mode, but can show up in SE mode. --HG-- extra : rebase_source : 613a69fe1d9834261e25a8cd340aa6b47578e1fe
2011-12-01X86: Fix a bad segmentation check for the stack segment.Gabe Black
--HG-- extra : rebase_source : 755f4f6eae52f88ed516a1f1ac9e2565725d89c1
2011-11-28SPARC: Minor style fix.Gabe Black
I forgot to fix this as well per Ali's feedback. --HG-- extra : rebase_source : e70d031cb5f91e2212a1a73ea1769bf0549b826c
2011-11-27SPARC: Isolate FP operations enough to prevent code/rounding mode reordering.Gabe Black
--HG-- extra : rebase_source : ee79ab89c5a707c1294f38abb84c60f8ef64196c
2011-11-20X86: Fix the constant detecting three byte opcodes in the predecoder.Gabe Black
--HG-- extra : rebase_source : b64c3d2348cb73177024695fb6e205d51bf1cda9
2011-11-03x86: Add microop for fenceNilay Vaish
This patch adds a new microop for memory barrier. The microop itself does nothing, but since it is marked as a memory barrier, the O3 CPU should flush all the pending loads and stores before the fence to the memory system.
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
And by "everything" I mean all the quick regressions.
2011-10-22SE: move page allocation from PageTable to ProcessSteve Reinhardt
PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable. The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process.
2011-10-22syscall_emul: implement MAP_FIXED option to mmap()Steve Reinhardt
2011-09-27Faults: Replace calls to genMachineCheckFault with M5PanicFault.Gabe Black
2011-09-27Faults: Add in generic faults that work like panics, warns, etc.Gabe Black
These faults take varargs to their constructors which they print into a string and pass to the M5DebugFault base class. They are basically faults wrapped around panics, faults, warns, and warnonce-es so that they happen only at commit.
2011-09-26ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.Gabe Black
By using an underscore, the "." is still available and can unambiguously be used to refer to members of a structure if an operand is a structure, class, etc. This change mostly just replaces the appropriate "."s with "_"s, but there were also a few places where the ISA descriptions where handling the extensions themselves and had their own regular expressions to update. The regular expressions in the isa parser were updated as well. It also now looks for one of the defined type extensions specifically after connecting "_" where before it would look for any sequence of characters after a "." following an operand name and try to use it as the extension. This helps to disambiguate cases where a "_" may legitimately be part of an operand name but not separate the name from the type suffix. Because leaving the "_" and suffix on the variable name still leaves a valid C++ identifier and all extensions need to be consistent in a given context, I considered leaving them on as a breadcrumb that would show what the intended type was for that operand. Unfortunately the operands can be referred to in code templates, the Mem operand in particular, and since the exact type of Mem can be different for different uses of the same template, that broke things.
2011-09-24SCons: Add a comment I forgot to add in earlier.Gabe Black
This comment was supposed to be added to an earlier change as part of review feedback, but I accidentally left it out when I pushed. Add it in now.
2011-09-24SCons: Make the ISA parser a source for its output files like the comments say.Gabe Black
There was a change a while ago that refactored some scons stuff which got rid of cpu_models.py but also accidentally got rid of the ISA parser as a source for its target files. That meant that changes which affected the parser wouldn't cause a rebuild unless they also changed one of the description files. This change fixes that.
2011-09-23X86: Move the MSR lookup table out of the TLB and into its own file.Gabe Black
Translating MSR addresses into MSR register indices took a lot of space in the TLB source and made looking around in that file awkward. This change moves the lookup into its own file to get it out of the way. It also changes it from a switch statement to a hash map which should hopefully be a little more efficient.
2011-09-19MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEMGabe Black
This change is a significant reorganization of the MIPS fault code that gets rid of duplication, fixes some bugs, doubtlessly introduces others, and adds names for the exception code constants.
2011-09-19MIPS, faults: Update how the PC is set.Gabe Black
2011-09-19MIPS: Get rid of skipFaultInstruction and setRestartAddress.Gabe Black
Neither of these functions were used.
2011-09-19MIPS: Use inheritance to consolidate class definitions.Gabe Black
2011-09-19MIPS: Always compile in setExceptionState, including in SE mode.Gabe Black
Also fix the newly exposed and preexisting compile errors. This code hasn't been exposed in a while, and it's not up to date with the rest of gem5.
2011-09-19MIPS: Consolidate TLB related faults.Gabe Black
Pass in a bool to indicate if the fault is from a store instead of having two different classes. The classes were also misleadingly named since loads are also processed by the DTB but should return ITB faults since they aren't stores. The TLB may be returning the wrong fault in this case, but I haven't looked at it closely.
2011-09-19MIPS: Get rid of the unused "count" field in FaultVals.Gabe Black
2011-09-19MIPS: Move the genMachineCheckFault function near MachineCheckFault.Gabe Black
Since they're so closely linked, they should be next to each other in the file.
2011-09-19MIPS: Consolidate the two AddressErrorFault variants.Gabe Black
2011-09-19Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.Gabe Black
These functions aren't called anywhere and are probably only theoretically useful.
2011-09-19MIPS: Get rid of cruft in the fault classes.Gabe Black
Get rid of Fault classes left over from when this file was copied from Alpha, and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of the old IntegerOverflowFault stub. The Integer version is what's actually in the manual, but the Arithmetic version had the implementation.
2011-09-19MIPS: Add constructors to the fault classes.Gabe Black
2011-09-19MIPS: Use the CRTP to streamline the Fault class definitions.Gabe Black
CRTP stands for the curiously recurring template pattern.
2011-09-19SPARC: Remove #if FULL_SYSTEMs from the ISA description.Gabe Black
2011-09-19MIPS: Get rid of #if style config checks in the ISA description.Gabe Black
2011-09-19MIPS: Guard SystemCallFault::invoke consistently.Gabe Black
Make sure it's declared iff it's also defined.
2011-09-19MIPS: Get rid of the unused (and partially defined) CacheError fault.Gabe Black
2011-09-19Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.Gabe Black
The remaining ones are more complicated and may require adjustments in other parts of the simulator.
2011-09-19X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.Gabe Black
The decoder now checks the value of FULL_SYSTEM in a switch statement to decide whether to return a real syscall instruction or one that triggers syscall emulation (or a panic in FS mode). The switch statement should devolve into an if, and also should be optimized out since it's based on constant input.
2011-09-19PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.Gabe Black
2011-09-18Pseudoinst: Add an initParam pseudo inst function.Gabe Black
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-09-13LSQ: Only trigger a memory violation with a load/load if the value changes.Ali Saidi
Only create a memory ordering violation when the value could have changed between two subsequent loads, instead of just when loads go out-of-order to the same address. While not very common in the case of Alpha, with an architecture with a hardware table walker this can happen reasonably frequently beacuse a translation will miss and start a table walk and before the CPU re-schedules the faulting instruction another one will pass it to the same address (or cache block depending on the dendency checking). This patch has been tested with a couple of self-checking hand crafted programs to stress ordering between two cores. The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-10MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.Deyuan Guo
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote debugging. Testing: Build gem5 for MIPS_SE and make gem5 wait at beginning: modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc; scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU ---- Build GDB-7.3 mips-cross: ./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/ make make install ---- Run: ./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches ./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello (gdb) target remote :7000 (gdb) info registers (gdb) disassemble (gdb) si (gdb) break main (gdb) c (gdb) quit Testing done.
2011-09-09StaticInst: Merge StaticInst and StaticInstBase.Gabe Black
Having two StaticInst classes, one nominally ISA dependent and the other ISA dependent, has not been historically useful and makes the StaticInst class more complicated that it needs to be. This change merges StaticInstBase into StaticInst.
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