Age | Commit message (Expand) | Author |
2011-08-19 | ARM: Mark some variables uncacheable until boot all CPUs are enabled. | Ali Saidi |
2011-08-19 | ARM: Add VExpress_E support with PCIe to gem5 | Ali Saidi |
2011-08-19 | ARM: Add support for Versatile Express boards | Ali Saidi |
2011-08-19 | ARM: Add support for DIV/SDIV instructions. | Ali Saidi |
2011-08-19 | Fix bugs due to interaction between SEV instructions and O3 pipeline | Geoffrey Blake |
2011-08-19 | ARM: Fix a memory leak with the table walker. | Ali Saidi |
2011-08-13 | X86: Use IsSquashAfter if an instruction could affect fetch translation. | Gabe Black |
2011-07-15 | ARM: Fix SWP/SWPB undefined instruction behavior | Wade Walker |
2011-07-15 | ARM: Add two unimplemented miscellaneous registers. | Wade Walker |
2011-07-11 | X86: implements copyRegs() function | Nilay Vaish |
2011-07-11 | ISA: Get rid of the unused mem_acc_type template parameter. | Gabe Black |
2011-07-07 | alpha:hwrei:rollback for o3 | Korey Sewell |
2011-07-05 | grammar: better encapsulation of a grammar and parsing | Nathan Binkert |
2011-07-05 | ISAs: Streamline some spots where Mem is used in the ISA descriptions. | Gabe Black |
2011-07-05 | ISA parser: Define operand types with a ctype directly. | Gabe Black |
2011-07-05 | ISA parser: Simplify operand type handling. | Gabe Black |
2011-07-02 | ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. | Gabe Black |
2011-07-02 | ISA: Use readBytes/writeBytes for all instruction level memory operations. | Gabe Black |
2011-07-02 | X86: Fix store microops so they don't drop faults in timing mode. | Gabe Black |
2011-06-28 | arch: print next upc correctly | Nilay Vaish |
2011-06-22 | mips: fix nmsub and nmadd definitions | Deyaun Guo |
2011-06-21 | X86: Eliminate an unused argument for building store microops. | Gabe Black |
2011-06-19 | mips: mark unaligned access flag as true | Korey Sewell |
2011-06-19 | inorder/dtb: make sure DTB translate correct address | Korey Sewell |
2011-06-19 | alpha: fix warn_once for prefetches | Korey Sewell |
2011-06-19 | alpha: naming for dtb faults | Korey Sewell |
2011-06-19 | alpha: make hwrei a control inst | Korey Sewell |
2011-06-19 | sparc: init. cache state in TLB | Korey Sewell |
2011-06-19 | cpus/isa: add a != operator for pcstate | Korey Sewell |
2011-06-17 | ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. | Gedare Bloom |
2011-06-16 | ARM: Handle case where new TLB size is different from previous TLB size. | Ali Saidi |
2011-06-16 | ARM: Fix memset on TLB flush and initialization | Chander Sudanthi |
2011-06-10 | sparc: don't use directcntrl branch flag | Korey Sewell |
2011-06-09 | sparc: compilation fixes for inorder | Korey Sewell |
2011-06-07 | ISA parser: Loosen the regular expressions matching filenames. | Gabe Black |
2011-06-02 | scons: rename TraceFlags to DebugFlags | Nathan Binkert |
2011-06-02 | copyright: clean up copyright blocks | Nathan Binkert |
2011-05-23 | syscall emul: fix Power Linux mmap constant, plus other cleanup | Steve Reinhardt |
2011-05-23 | config: revamp x86 config to avoid appending to SimObjectVectors | Steve Reinhardt |
2011-05-23 | O3: Fix issue with interrupts/faults occuring in the middle of a macro-op | Geoffrey Blake |
2011-05-18 | gcc: fix an uninitialized variable warning from G++ 4.5 | Nathan Binkert |
2011-05-13 | ARM: Generate condition code setting code based on which codes are set. | Ali Saidi |
2011-05-13 | ARM: Construct the predicate test register for more instruction programatically. | Ali Saidi |
2011-05-13 | ARM: Further break up condition code into NZ, C, V bits. | Ali Saidi |
2011-05-13 | ARM: Remove the saturating (Q) condition code from the renamed register. | Ali Saidi |
2011-05-13 | ARM: Break up condition codes into normal flags, saturation, and simd. | Ali Saidi |
2011-05-13 | Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. | Chander Sudanthi |
2011-05-13 | ARM: Better RealView/Versatile EB platform support. | Chander Sudanthi |
2011-05-06 | X86: Fix the Lldt instructions so they load the ldtr and not the tr. | Gabe Black |
2011-05-04 | ARM: Add support for loading the a bootloader and configuring parameters for it | Ali Saidi |