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path: root/src/arch
AgeCommit message (Expand)Author
2016-09-16hsail: Fix disassembly of load instruction with 3 destination operandsAlexandru Dutu
2016-09-16gpu-compute: Refactoring Wavefront::dynWaveIdAlexandru Dutu
2016-09-16gpu-compute: Wavefront refactoringAlexandru Dutu
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
2016-09-13x86: Force strict ordering for memory mapped m5opsMichael LeBeane
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-08-05sim: fix issues with pwrite(); don't enable fstatfsTony Gutierrez
2016-08-04x86, sim: add some syscalls to X86Tony Gutierrez
2016-08-02arm: refactor page table walkingCurtis Dunham
2016-08-02arm: warn not fail on use of missing miscreg CNTHCTL_EL2Dylan Johnson
2016-08-02arm: Check TLB stage 2 permissions in AArch64Dylan Johnson
2016-08-02arm: correctly assign faulting IPA's to HPFAR_EL2Dylan Johnson
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
2016-08-02arm: Fix stage 2 memory attribute checking in AArch64Dylan Johnson
2016-08-02arm: Fix trapping to Hypervisor during MSR/MRS read/writeDylan Johnson
2016-08-02arm: Fix secure state checking in various placesDylan Johnson
2016-08-02arm: Fix stage 2 determination in table walkerDylan Johnson
2016-08-02arm: Refactor aarch64 table walk logic to remove redundancyDylan Johnson
2016-08-02arm: Add check to fault routing for hypervisor/virtualizationDylan Johnson
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
2016-08-02arm: add stage2 translation supportDylan Johnson
2016-08-02arm: enable EL2 supportCurtis Dunham
2016-08-02arm: invalidate TLB miscreg cache on modification of HSCTLRDylan Johnson
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
2016-07-21isa: Modify get/check interrupt routinesMitch Hayenga
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
2016-06-20arm: Mark uninitialized new TLB entries as not validNikos Nikoleris
2016-06-20kern, arm: Dump dmesg on kernel panic/oopsAndreas Sandberg
2016-06-18gpu-compute: Fixed a bug in decoding Atomic STTuan Ta
2016-06-09gpu-compute: parametrize Wavefront sizejkalamat
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-06-02arm: refactor page table format determinationCurtis Dunham
2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
2016-06-02arm: Correctly check FP/SIMD access permission in aarch32Andreas Sandberg
2016-05-31arm: Enable LPAE support by defaultAndreas Sandberg
2016-05-31arm: Correctly check translation mode (aarch64/aarch32)Andreas Sandberg
2016-05-27arm: Use the target EL state when determining fault formatAndreas Sandberg
2016-05-26arm: Fix incorrect TLB permission check in aarch32Andreas Sandberg
2016-05-26arm: Make EL checks available in SE modeAndreas Sandberg
2016-05-26arm: Fix heap overflow issue in Neon64Load operationAndreas Hansson
2016-05-19config, x86: Properly space pad the X86IntelMPBus Entry descriptionsBjoern A. Zeeb
2016-05-19x86, dev: properly space the APIC registersBjoern A. Zeeb
2016-04-27arm: Remove BreakPCEvent on guest kernel panicAndreas Sandberg
2016-04-27kvm, arm: Make GIC interrupt lines configurableAndreas Sandberg
2016-04-27kvm, arm: Refactor KVM GIC deviceAndreas Sandberg
2016-04-15arm,dev: remove PMU assertion hit on resetBjoern A. Zeeb
2016-04-13misc: Fix issues flagged by gcc 6Andreas Hansson
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
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