gem5 - gem5

Age	Commit message (Collapse)	Author
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
	This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2011-01-07	scons: show sources and targets when building, and colorize output.	Steve Reinhardt
	I like the brevity of Ali's recent change, but the ambiguity of sometimes showing the source and sometimes the target is a little confusing. This patch makes scons typically list all sources and all targets for each action, with the common path prefix factored out for brevity. It's a little more verbose now but also more informative. Somehow Ali talked me into adding colors too, which is a whole 'nother story.
2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
	Ran all the source files through 'perl -pi' with this script: s\|\s(};?\s)?/\\s(end\s)?namespace\s(\S+)\s\/(\s})?\|} // namespace $3\|; s\|\s};?\s//\s(end\s)?namespace\s(\S+)\s\|} // namespace $2\n\|; s\|\s};?\s//\s(\S+)\snamespace\s\|} // namespace $1\n\|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2010-12-20	Style: Replace some tabs with spaces.	Gabe Black

2010-12-09	ARM: Take advantage of new PCState syntax.	Gabe Black

2010-12-09	ARM: Get rid of some unused FP operands.	Gabe Black

2010-12-08	Alpha: Take advantage of new PCState syntax.	Gabe Black

2010-12-08	MIPS: Take advantage of new PCState syntax.	Gabe Black

2010-12-08	POWER: Take advantage of new PCState syntax.	Gabe Black

2010-12-08	SPARC: Take advantage of new PCState syntax.	Gabe Black

2010-12-08	X86: Take advantage of new PCState syntax.	Gabe Black

2010-12-07	ISA: Get the parser to support pc state components more elegantly.	Gabe Black

2010-12-07	O3: Support squashing all state after special instruction	Ali Saidi
	For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply marking the instruction as Serializing isn't enough beacuse that only stops rename. This provides a mechanism to squash all the instructions and refetch them
2010-12-07	O3: Make all instructions that write a misc. register not perform the write ↵	Giacomo Gabrielli
	until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong

2010-12-07	ARM: Support switchover with hardware table walkers	Ali Saidi

2010-11-23	X86: Obey the PCD (cache disable) bit in the page tables.	Gabe Black

2010-11-22	X86: Mark IO space accesses as uncachable.	Gabe Black

2010-11-19	SCons: Support building without an ISA	Ali Saidi

2010-11-15	O3: Make O3 support variably lengthed instructions.	Gabe Black

2010-11-15	ARM: Add comment about the organization of the IT state register	Ali Saidi

2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli

2010-11-15	ARM: Return an FailUnimp instruction when an unimplemented CP15 register is ↵	Ali Saidi
	accessed. Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation.
2010-11-15	SCons: Cleanup SCons output during compile	Ali Saidi

2010-11-15	ARM: Add support for GDB on ARM	William Wang
	--HG-- rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc
2010-11-15	ARM: Make utility.hh meet style guidelines	Ali Saidi

2010-11-15	ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.	Ali Saidi

2010-11-15	ARM: Add support for switching CPUs	Ali Saidi

2010-11-15	ARM: Use the correct delete operator for RFE	Ali Saidi

2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
	Previously the SRS instruction attempted to writeback in initiateAcc() which worked until a recent change, but was incorrect.
2010-11-15	ARM: Do something predictable for an UNPREDICTABLE branch.	Ali Saidi

2010-11-11	SPARC: Clean up some historical style issues.	Gabe Black

2010-11-08	X86: Fix X86_FS compilation.	Gabe Black

2010-11-08	ARM: Add some TLB statistics for ARM	Ali Saidi

2010-11-08	ARM: Add checkpointing support	Ali Saidi

2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi

2010-11-08	ARM: Keep the warnings to a minimum.	Ali Saidi
	These warnings still need to be addresses, but pages of them is counterproductive.
2010-11-08	ARM: Don't return the result of a table walk the same cycle it's completed.	Ali Saidi
	The L1 cache may have been accessed to provide this data, which confuses it, if it ends up being accesses twice in one cycle. Instead wait 1 tick which will force the timing simple CPU to forward to its next clock cycle when the translation completes. Also prevent multiple outstanding table walks from occuring at once.
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
	This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path.
2010-11-08	ARM: Make all ARM uops delayed commit.	Ali Saidi

2010-11-08	sim: Use forward declarations for ports.	Ali Saidi
	Virtual ports need TLB data which means anything touching a file in the arch directory rebuilds any file that includes system.hh which in everything.
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
	This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-29	X86: Fault on divide by zero instead of panicing.	Gabe Black

2010-10-29	X86: Make syscalls also serialize after.	Gabe Black

2010-10-22	X86: Make nop a regular, non-microcoded instruction.	Gabe Black
	Code in the CPUs that need a nop to carry a fault can't easily deal with a microcoded nop. This instruction format provides for one that isn't. --HG-- rename : src/arch/x86/isa/formats/syscall.isa => src/arch/x86/isa/formats/nop.isa
2010-10-22	X86: Implement genMachineCheckFault.	Gabe Black
	Even though this shouldn't ever be used, it might get called speculatively and shouldn't panic.
2010-10-22	X86: Make syscall instructions non-speculative in SE.	Gabe Black

2010-10-22	ISA: Simplify various implementations of completeAcc.	Gabe Black

2010-10-22	ARM: Don't pretend to writeback registers in initiateAcc.	Gabe Black

2010-10-16	Mem: Reclaim some request flags used by MIPS for alignment checking.	Gabe Black
	These flags were being used to identify what alignment a request needed, but the same information is available using the request size. This change also eliminates the isMisaligned function. If more complicated alignment checks are needed, they can be signaled using the ASI_BITS space in the flags vector like is currently done with ARM.