| Age | Commit message (Expand) | Author |
|---|
| 2017-08-01 | kvm, arm: Switch to the device EQ when accessing ISA devices | Andreas Sandberg |
| 2017-08-01 | arch-arm: Switch to DTOnly as the default machine type | Andreas Sandberg |
| 2017-07-17 | sim, x86: Make clone a virtual function | Sean Wilson |
| 2017-07-17 | x86: Add stats to X86 TLB | Swapnil Haria |
| 2017-07-17 | riscv: Define register index constants using literals | Alec Roelke |
| 2017-07-14 | riscv: Disambiguate between the C and C++ versions of isnan and isinf. | Gabe Black |
| 2017-07-14 | riscv: Fix bugs with RISC-V decoder and detailed CPUs | Alec Roelke |
| 2017-07-14 | riscv: Add unused attribute to some registers.hh constants | Alec Roelke |
| 2017-07-13 | arch-arm: fix ldm of pc interswitching branch | Gedare Bloom |
| 2017-07-12 | mips, x86: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-11 | arch-riscv: Add support for compressed extension RV64C | Alec Roelke |
| 2017-07-11 | arch-riscv: Restructure ISA description | Alec Roelke |
| 2017-07-10 | arch-arm: Support PMU evens in the 0x4000-0x4040 range | Jose Marinho |
| 2017-07-07 | kvm, arm: don't create interrupt events while saving GIC state | Curtis Dunham |
| 2017-07-07 | kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC | Andreas Sandberg |
| 2017-07-05 | arch: ISA parser additions of vector registers | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch: added generic vector register | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2017-07-05 | arm,kvm: update CP15 timer model when exiting Kvm | Curtis Dunham |
| 2017-07-05 | kvm: move Kvm check from ARM Kvm GIC to System | Curtis Dunham |
| 2017-06-22 | arm,sim: fix context switch stats dumps for ARM64/Linux | Paul Rosenfeld |
| 2017-06-20 | sim, x86: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
| 2017-06-20 | arm: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
| 2017-06-15 | x86: Add consistent overrides to process.hh | Sean Wilson |
| 2017-06-15 | x86: Fixed remote debugging of simulated code | Matthias Hille |
| 2017-05-26 | x86: Rework how VEX prefixes are decoded. | Gabe Black |
| 2017-05-25 | x86: sim: Make 32 bit x86 processes work again. | Gabe Black |
| 2017-05-24 | arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU | Andreas Sandberg |
| 2017-05-23 | arch-riscv: Fix bad stack initialization | Alec Roelke |
| 2017-05-23 | arch-arm: Fix some poorly done type max and min in NEON | Rekai Gonzalez-Alberquilla |
| 2017-05-19 | base, sim, arch: Fix clang 5.0 warnings | Andreas Sandberg |
| 2017-05-18 | base: Refactor the GDB code. | Gabe Black |
| 2017-05-18 | syscall_emul, riscv: add override keyword to RISCV Process class | Brandon Potter |
| 2017-05-16 | x86: Fix the multiplication microops. | Gabe Black |
| 2017-05-12 | arm: Remove unused DumpStatsPCEventF class in FreeBSD system | Andreas Sandberg |
| 2017-05-10 | scons: Use the generalized switching headers on the GPU ISA. | Gabe Black |
| 2017-05-10 | scons: arch: Generalize the switching header code. | Gabe Black |
| 2017-05-09 | arm: Add support for memory-mapped m5ops | Andreas Sandberg |
| 2017-05-09 | kvm, arm: Fix incorrect PSTATE sync | Andreas Sandberg |
| 2017-05-02 | python: Use PyBind11 instead of SWIG for Python wrappers | Andreas Sandberg |
| 2017-05-01 | arch-sparc: Fix wrong indentation causing warnings for gcc 6 | Nikos Nikoleris |
| 2017-04-18 | x86: fixed branching() computation for branch uops | Santi Galan |
| 2017-04-11 | riscv: Fix crashes with large or frequent mmaps | Alec Roelke |
| 2017-04-05 | riscv: fix Linux problems with LR and SC ops | Alec Roelke |
| 2017-04-05 | riscv: fix compatibility with Linux toolchain | Alec Roelke |
| 2017-04-05 | riscv: add remote gdb support | Alec Roelke |
| 2017-04-05 | riscv: fix error on memory op address overflow | Alec Roelke |
| 2017-04-05 | riscv: enable unaligned memory accesses | Alec Roelke |
