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value if they don't actually execute.
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This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
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It still needs to zero the overflow and carry flags to be correct.
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Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
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could check.
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Define bitfields, indices, etc.
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This is stored in the integer register file so that it can be renamed, but it should be a misc reg.
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rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa
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src/arch/mips/isa/decoder.isa:
commment out deret instruction for now...
src/arch/mips/isa/formats/fp.isa:
edit fp format
src/arch/mips/isa/formats/mem.isa:
fix for basic store instructions
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ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality...
src/arch/isa_parser.py:
add back deleted writeback in Control Operand
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src/arch/mips/SConscript:
"mips import pt.1".
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/newmem-o3-micro
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro
src/cpu/o3/fetch_impl.hh:
hand merge
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an "ID", and also added support for symbols.
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displacement.
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an lea microop, move EmulEnv into it's own .cc and .hh.
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