gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-07	arch: Move the ISA object to a separate section	Andreas Sandberg
2013-01-07	arch: Add support for invalidating TLBs when draining	Andreas Sandberg
2013-01-07	arch: Fix broken M5VarArgsFault initialization	Andreas Sandberg
2013-01-07	base: Encapsulate the underlying fields in AddrRange	Andreas Hansson
2013-01-07	arm: Make ID registers ISA parameters	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2013-01-07	o3: Fix issue with LLSC ordering and speculation	Ali Saidi
2013-01-04	Decoder: Remove the thread context get/set from the decoder.	Gabe Black
2013-01-04	X86: Move address based decode caching in front of the predecoder.	Gabe Black
2013-01-04	SPARC: Keep a copy of the current ASI in the decoder.	Gabe Black
2013-01-04	ARM: Keep a copy of the fpscr len and stride fields in the decoder.	Gabe Black
2012-12-30	x86: implement x87 fp instruction fnstsw	Nilay Vaish
2012-12-30	x86: implement x87 fp instruction fsincos	Nilay Vaish
2012-12-12	arm: set uopSet_uop as conditional or unconditional control	Nathanael Premillieu
2012-12-12	arm: set movret_uop as conditional or unconditional control	Nathanael Premillieu
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	mips: Remove unused Python file	Andreas Sandberg
2012-11-02	ARM: dump stats and process info on context switches	Dam Sunwoo
2012-11-02	ISA: generic Linux thread info support	Dam Sunwoo
2012-10-25	arm: Use table walker clock that is inherited from CPU	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Checkpoint: Make system serialize call children	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-09-25	ARM: added support for flattened device tree blobs	Dam Sunwoo
2012-09-25	ARM: Squash outstanding walks when instructions are squashed.	Ali Saidi
2012-09-25	arm: Use a static_assert to test that miscRegName[] is complete	Andreas Sandberg
2012-09-25	ARM: Inst writing to cntrlReg registers not set as control inst	Nathanael Premillieu
2012-09-25	ARM: Predict target of more instructions that modify PC.	Ali Saidi
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-11	X86: make use of register predication	Nilay Vaish
2012-09-11	x86: Add a separate register for D flag bit	Nilay Vaish
2012-06-03	ISA Parser: Allow predication of source and destination registers	Nilay Vaish
2012-09-10	NetBSD: Build on NetBSD	Palle Lyckegaard
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-21	Device: Remove overloaded pio_latency parameter	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-08-16	Alpha System: override startup(), instead of loadState()	Nilay Vaish
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-08-15	sysemul: bump all linux versions of for syscal emulation to 3.0.	Ali Saidi
2012-08-06	syscall emulation: Enabled getrlimit and getrusage for x86.	Marc Orr
2012-08-06	syscall emulation: Clean up ioctl handling, and implement for x86.	Marc Orr
2012-07-27	ARM: fix value of MISCREG_CTR returned by readMiscReg()	Anthony Gutierrez
2012-07-22	X86 CPUID: Return false if unknown processor family	Nilay Vaish
2012-07-11	x86: added page size in bytes tlb entry function	Brad Beckmann
2012-07-10	syscall emulation: Add the futex system call.	Marc Orr
2012-07-10	x86: logSize and lruSeq are now optional ckpt params	Brad Beckmann
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson