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AgeCommit message (Expand)Author
2018-01-20x86, mem: Pass the multi level page table layout in as a parameter.Gabe Black
2018-01-20arch, mem: Make the page table lookup function return a pointer.Gabe Black
2018-01-20arm, base: Generalize and move the BitUnion hash struct.Gabe Black
2018-01-20base: Rework bitunions so they can be more flexible.Gabe Black
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
2018-01-19arch, mem, sim: Consolidate and rename the SE mode page table classes.Gabe Black
2018-01-16arch-riscv: Fix floating-poing op classesAlec Roelke
2018-01-16arch-riscv: Fix floating-point conversion bugsAlec Roelke
2018-01-15arch: Fix a fatal_if in most of the arch's process classes.Gabe Black
2018-01-11arch-riscv: Don't crash when printing unknown CSRsAlec Roelke
2018-01-11arm, power: Make the python TLB simobjects inherit from BaseTLB.Gabe Black
2018-01-11arch,mem: Remove the default value for page size.Gabe Black
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
2018-01-10style: change C/C++ source permissions to noexecBKP
2018-01-10arch-riscv: Make use of ImmOp's polymorphismAlec Roelke
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
2018-01-09cpu, power: Get rid of the remnants of the EA computation insts.Gabe Black
2018-01-09arm: Make translateFunctional override the base implementation.Gabe Black
2018-01-05arch-riscv: Ignore sched_yield syscall in SE modeTuan Ta
2018-01-05arch-riscv: Ignore set_robust_list and get_robust_list syscallsTuan Ta
2018-01-05arch-riscv: Add an implementation of set_tid_address syscall in RISCVTuan Ta
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke
2018-01-04arch-riscv: Remove "magic" syscall number constantAlec Roelke
2017-12-23alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.Gabe Black
2017-12-23riscv,x86: Stop using the arch Nop machine instruction unnecessarily.Gabe Black
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-21arch-arm: Fixed WFE/WFI trapping behaviourGiacomo Travaglini
2017-12-21arch-arm: Hyp routed undef fault need to change its syndromeGiacomo Travaglini
2017-12-21arch-arm: Fix StaticInst encoding() methodGiacomo Travaglini
2017-12-19arch-arm: Instruction size methods in StaticInst classGiacomo Travaglini
2017-12-19arch-arm: Change casting type from reinterpret to staticGiacomo Travaglini
2017-12-14arch-riscv: Define AT_RANDOM properlyAlec Roelke
2017-12-14arch-riscv: Increase maximum stack sizeAlec Roelke
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-12-14x86: Use operand size 4 when it would be 2 for cmpxchg8b.Gabe Black
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
2017-12-13x86: Rework how "split" loads/stores are handled.Gabe Black
2017-12-08arm: Change access permission in TPIDRURO and TPIDRURWGiacomo Travaglini
2017-12-08x86,misc: add additional info on faulting X86 instruction, fetched PCMatt Sinclair
2017-12-07arch-riscv: Move compressed ops out of ISAAlec Roelke
2017-12-06x86: Split apart x87's FSW and TOP, and add a missing break.Gabe Black
2017-12-05x86: LOOP's operand size defaults to 64 bits in 64 bit mode.Gabe Black
2017-12-05arm: Add support for the dc {civac, cvac, cvau, ivac} instrNikos Nikoleris
2017-12-05arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructionsNikos Nikoleris
2017-12-05arm: Add CMO support for Non-Cacheable memoryNikos Nikoleris
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-12-01arm: Enable ns registers access in secure modeGiacomo Travaglini
2017-11-30arch-riscv: use sext rather than manual masksAlec Roelke
2017-11-30arch-riscv: Remove spaces around ea_codeAlec Roelke