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AgeCommit message (Expand)Author
2018-02-07arch-arm: Turn dc ivac to dc civac when some conditions are metNikos Nikoleris
2018-02-07arch-arm: Fix printing of the data cache maintenance instructionsNikos Nikoleris
2018-02-07arch-arm: Fix cache line size for cache maintenace instNikos Nikoleris
2018-02-07arch-arm: Fault when dc ivac is executed from EL0Nikos Nikoleris
2018-02-07arch-arm: Change function name for banked miscregsGiacomo Travaglini
2018-02-07arch-arm: Fix AArch32 SETEND InstructionGiacomo Travaglini
2018-02-07arch-arm: Correct Illegal Exception Return detectionGiacomo Travaglini
2018-02-07arch-arm: ELUsingAArch32K from armarm pseudocodeGiacomo Travaglini
2018-02-07arch-arm: isSecureBelow from armarm pseudocodeGiacomo Travaglini
2018-02-07arch-arm: Fix incorrect assumptions in ELIs64Chuan Zhu
2018-02-05arch-arm: Removing Serializing flag from ISBGiacomo Travaglini
2018-02-01alpha: fix for no 'break' in the case statementSujay Phadke
2018-01-31arch-x86: consistent style of comments in system filesChristian Menard
2018-01-30arch-x86: Granularity bit and segment limitMaximilian Stein
2018-01-29riscv: Add overrides to various StaticInst methods.Gabe Black
2018-01-29arch-arm: understandably initialize register permissionsCurtis Dunham
2018-01-29arm: extend MiscReg metadata structuresCurtis Dunham
2018-01-29arch-arm: understandably initialize register mappingsCurtis Dunham
2018-01-29arm: DT autogeneration - Generate memory nodeGlenn Bergmans
2018-01-29arm: DT autogeneration - Device Tree generation methodsGlenn Bergmans
2018-01-23arch-x86: Adding clflush, clflushopt, clwb instructionsSwapnil Haria
2018-01-23arch: Remove the "arch/tlb.hh" switching header.Gabe Black
2018-01-23tarch, mem: Abstract the data stored in the SE page tables.Gabe Black
2018-01-23x86, mem: Rewrite the multilevel page table class.Gabe Black
2018-01-20x86, mem: Don't try to force physical addresses on the system.Gabe Black
2018-01-20x86, mem: Get rid of PageTableOps::getBasePtr.Gabe Black
2018-01-20x86, mem: Pass the multi level page table layout in as a parameter.Gabe Black
2018-01-20arch, mem: Make the page table lookup function return a pointer.Gabe Black
2018-01-20arm, base: Generalize and move the BitUnion hash struct.Gabe Black
2018-01-20base: Rework bitunions so they can be more flexible.Gabe Black
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
2018-01-19arch, mem, sim: Consolidate and rename the SE mode page table classes.Gabe Black
2018-01-16arch-riscv: Fix floating-poing op classesAlec Roelke
2018-01-16arch-riscv: Fix floating-point conversion bugsAlec Roelke
2018-01-15arch: Fix a fatal_if in most of the arch's process classes.Gabe Black
2018-01-11arch-riscv: Don't crash when printing unknown CSRsAlec Roelke
2018-01-11arm, power: Make the python TLB simobjects inherit from BaseTLB.Gabe Black
2018-01-11arch,mem: Remove the default value for page size.Gabe Black
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
2018-01-10style: change C/C++ source permissions to noexecBKP
2018-01-10arch-riscv: Make use of ImmOp's polymorphismAlec Roelke
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
2018-01-09cpu, power: Get rid of the remnants of the EA computation insts.Gabe Black
2018-01-09arm: Make translateFunctional override the base implementation.Gabe Black
2018-01-05arch-riscv: Ignore sched_yield syscall in SE modeTuan Ta
2018-01-05arch-riscv: Ignore set_robust_list and get_robust_list syscallsTuan Ta
2018-01-05arch-riscv: Add an implementation of set_tid_address syscall in RISCVTuan Ta
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke
2018-01-04arch-riscv: Remove "magic" syscall number constantAlec Roelke
2017-12-23alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.Gabe Black