gem5 - gem5

Age	Commit message (Expand)	Author
2017-10-31	x86: Fix VEX instruction decoding.	Gabe Black
2017-10-20	arch-arm: RBIT instruction using mirroring func	Giacomo Travaglini
2017-10-17	scons: Stop generating inc.d in the isa parser.	Gabe Black
2017-10-17	arch-arm: Fix inverted 32/64-bit check in GDB	Boris Shingarov
2017-10-13	arch-arm: Signal an event when executing store exclusives	Nikos Nikoleris
2017-10-13	mem: Signal the local monitor when clearing the global monitor	Nikos Nikoleris
2017-09-27	arch-x86: fix CondInst decoding for MOV to Control Registers	Bjoern A. Zeeb
2017-09-27	arch: change panic for Vector traceData to warn_once	Bjoern A. Zeeb
2017-09-21	alpha: Move some initialization logic from loadState into unserialize.	Gabe Black
2017-09-20	kvm: arm: Get rid of functions which just wrap the subclasses version.	Gabe Black
2017-09-11	stats: Move the swpipl function into the Alpha kernel stats.	Gabe Black
2017-09-11	stats: Get rid of some kernel stats related cruft.	Gabe Black
2017-08-30	arch-arm: Only increment SW PMU counters on writes to PMSWINC	Jose Marinho
2017-08-30	arch-arm: Add missing override keywords in fault.hh	Andreas Sandberg
2017-08-30	arch-x86: Add missing override in the X86 TLB	Andreas Sandberg
2017-08-30	arch-sparc: Add a FaultVals instantiation for VecDisabled	Andreas Sandberg
2017-08-30	arch-alpha: Add missing overrides	Andreas Sandberg
2017-08-28	x86: Use the new CondInst format for moves to/from control registers.	Gabe Black
2017-08-28	x86: Add a "CondInst" format for conditionally decoded instructions.	Gabe Black
2017-08-01	arch-arm: Use named constants for m5op instructions	Andreas Sandberg
2017-08-01	kvm, arm: Switch to the device EQ when accessing ISA devices	Andreas Sandberg
2017-08-01	arch-arm: Switch to DTOnly as the default machine type	Andreas Sandberg
2017-07-17	sim, x86: Make clone a virtual function	Sean Wilson
2017-07-17	x86: Add stats to X86 TLB	Swapnil Haria
2017-07-17	riscv: Define register index constants using literals	Alec Roelke
2017-07-14	riscv: Disambiguate between the C and C++ versions of isnan and isinf.	Gabe Black
2017-07-14	riscv: Fix bugs with RISC-V decoder and detailed CPUs	Alec Roelke
2017-07-14	riscv: Add unused attribute to some registers.hh constants	Alec Roelke
2017-07-13	arch-arm: fix ldm of pc interswitching branch	Gedare Bloom
2017-07-12	mips, x86: Refactor some Event subclasses into lambdas	Sean Wilson
2017-07-11	arch-riscv: Add support for compressed extension RV64C	Alec Roelke
2017-07-11	arch-riscv: Restructure ISA description	Alec Roelke
2017-07-10	arch-arm: Support PMU evens in the 0x4000-0x4040 range	Jose Marinho
2017-07-07	kvm, arm: don't create interrupt events while saving GIC state	Curtis Dunham
2017-07-07	kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC	Andreas Sandberg
2017-07-05	arch: ISA parser additions of vector registers	Rekai Gonzalez-Alberquilla
2017-07-05	cpu: Added interface for vector reg file	Rekai Gonzalez-Alberquilla
2017-07-05	arch: added generic vector register	Rekai Gonzalez-Alberquilla
2017-07-05	cpu: Simplify the rename interface and use RegId	Rekai Gonzalez-Alberquilla
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
2017-07-05	arm,kvm: update CP15 timer model when exiting Kvm	Curtis Dunham
2017-07-05	kvm: move Kvm check from ARM Kvm GIC to System	Curtis Dunham
2017-06-22	arm,sim: fix context switch stats dumps for ARM64/Linux	Paul Rosenfeld
2017-06-20	sim, x86: Replace EventWrapper use with EventFunctionWrapper	Sean Wilson
2017-06-20	arm: Replace EventWrapper use with EventFunctionWrapper	Sean Wilson
2017-06-15	x86: Add consistent overrides to process.hh	Sean Wilson
2017-06-15	x86: Fixed remote debugging of simulated code	Matthias Hille
2017-05-26	x86: Rework how VEX prefixes are decoded.	Gabe Black
2017-05-25	x86: sim: Make 32 bit x86 processes work again.	Gabe Black
2017-05-24	arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU	Andreas Sandberg