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AgeCommit message (Expand)Author
2016-10-26hsail,gpu-compute: fixes to appease clang++Tony Gutierrez
2016-10-26dev: Add m5 op to toggle synchronization for dist-gem5.Michael LeBeane
2016-10-26gpu-compute: support in-order data delivery in GM pipeTony Gutierrez
2016-10-26gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()Tony Gutierrez
2016-10-26gpu-compute, hsail: make the PC a byte address, not an instruction indexTony Gutierrez
2016-10-26gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WFTony Gutierrez
2016-10-26gpu-compute, hsail: call discardFetch() from the WFTony Gutierrez
2016-10-26hsail, gpu-compute: remove doGm/SmReturn add completeAccTony Gutierrez
2016-10-26gpu-compute: remove inst enums and use bit flag for attributesTony Gutierrez
2016-10-26gpu-compute: move disassemle() implementation to GPUStaticInstTony Gutierrez
2016-10-26gpu-compute, arch: add some methods to the base inst classes for ISA supportTony Gutierrez
2016-10-15cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClassFernando Endo
2016-10-13isa,arm: Add missing AArch32 FP instructionsMitch Hayenga
2016-10-04kvm: Adding details to kvm page fault in x86Alexandru Dutu
2016-09-16hsail: Fix disassembly of load instruction with 3 destination operandsAlexandru Dutu
2016-09-16gpu-compute: Refactoring Wavefront::dynWaveIdAlexandru Dutu
2016-09-16gpu-compute: Wavefront refactoringAlexandru Dutu
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
2016-09-13x86: Force strict ordering for memory mapped m5opsMichael LeBeane
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-08-05sim: fix issues with pwrite(); don't enable fstatfsTony Gutierrez
2016-08-04x86, sim: add some syscalls to X86Tony Gutierrez
2016-08-02arm: refactor page table walkingCurtis Dunham
2016-08-02arm: warn not fail on use of missing miscreg CNTHCTL_EL2Dylan Johnson
2016-08-02arm: Check TLB stage 2 permissions in AArch64Dylan Johnson
2016-08-02arm: correctly assign faulting IPA's to HPFAR_EL2Dylan Johnson
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
2016-08-02arm: Fix stage 2 memory attribute checking in AArch64Dylan Johnson
2016-08-02arm: Fix trapping to Hypervisor during MSR/MRS read/writeDylan Johnson
2016-08-02arm: Fix secure state checking in various placesDylan Johnson
2016-08-02arm: Fix stage 2 determination in table walkerDylan Johnson
2016-08-02arm: Refactor aarch64 table walk logic to remove redundancyDylan Johnson
2016-08-02arm: Add check to fault routing for hypervisor/virtualizationDylan Johnson
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
2016-08-02arm: add stage2 translation supportDylan Johnson
2016-08-02arm: enable EL2 supportCurtis Dunham
2016-08-02arm: invalidate TLB miscreg cache on modification of HSCTLRDylan Johnson
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
2016-07-21isa: Modify get/check interrupt routinesMitch Hayenga
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
2016-06-20arm: Mark uninitialized new TLB entries as not validNikos Nikoleris
2016-06-20kern, arm: Dump dmesg on kernel panic/oopsAndreas Sandberg
2016-06-18gpu-compute: Fixed a bug in decoding Atomic STTuan Ta
2016-06-09gpu-compute: parametrize Wavefront sizejkalamat
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-06-02arm: refactor page table format determinationCurtis Dunham
2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
2016-06-02arm: Correctly check FP/SIMD access permission in aarch32Andreas Sandberg