| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-08-25 | ARM: Fix VFP enabled checks for mem instructions | Ali Saidi | |
| 2010-08-25 | ARM: Seperate out the renamable bits in the FPSCR. | Gabe Black | |
| 2010-08-25 | ARM: Eliminate some unused enums. | Gabe Black | |
| 2010-08-25 | ARM: Fix type comparison warnings in Neon. | Gabe Black | |
| 2010-08-25 | ARM: Implement CPACR register and return Undefined Instruction when FP ↵ | Gabe Black | |
| access is disabled. | |||
| 2010-08-25 | ARM: Implement all ARM SIMD instructions. | Gabe Black | |
| 2010-08-25 | ARM: Expand the mode checking utility functions. | Gabe Black | |
| inUserMode now can take either a threadcontext or a CPSR value directly. If given a thread context it just extracts the CPSR and calls the other version. An inPrivelegedMode function was also implemented which just returns the opposite of inUserMode. | |||
| 2010-08-23 | X86: Create a directory for files that define register indexes. | Gabe Black | |
| This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh | |||
| 2010-08-23 | Power: Get rid of unused checkFpEnableFault. | Gabe Black | |
| This function was brought in from another ISA and doesn't actually do anything or get used. | |||
| 2010-08-23 | ISA: Get rid of old, unused utility functions cluttering up the ISAs. | Gabe Black | |
| 2010-08-23 | X86: Get rid of the flagless microop constructor. | Gabe Black | |
| This will reduce clutter in the source and hopefully speed up compilation. | |||
| 2010-08-23 | X86: Make the TLB fault instead of panic when something is unmapped in SE mode. | Gabe Black | |
| The fault object, if invoked, would then panic. This is a bit less direct, but it means speculative execution won't panic the simulator. | |||
| 2010-08-23 | X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR. | Gabe Black | |
| --HG-- rename : src/arch/x86/types.hh => src/arch/x86/types.cc | |||
| 2010-08-23 | X86: Define a noop ExtMachInst. | Gabe Black | |
| 2010-08-23 | X86: Mark serializing macroops and regular instructions as such. | Gabe Black | |
| 2010-08-23 | X86: Add a .serializing directive that makes a macroop serializing. | Gabe Black | |
| This directive really just tells the macroop to set IsSerializing and IsSerializeAfter on its final microop. | |||
| 2010-08-23 | X86: Consolidate extra microop flags into one parameter. | Gabe Black | |
| This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor. | |||
| 2010-08-23 | ARM: Improve printing of uop disassembly. | Min Kyu Jeong | |
| 2010-08-23 | ARM: Clean up flattening for SPSR adding | Min Kyu Jeong | |
| 2010-08-23 | ARM: Implement DBG instruction that doesn't do much for now. | Gene Wu | |
| 2010-08-23 | MEM: Make CLREX a first class request operation and clear locks in caches ↵ | Gene Wu | |
| when it in received | |||
| 2010-08-23 | ARM: Make sure that software prefetch instructions can't change the state of ↵ | Gene Wu | |
| the TLB | |||
| 2010-08-23 | ARM: Don't write tracedata on writes, it might have been freed already. | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX init/complete acc methods | Gene Wu | |
| 2010-08-23 | ARM: Fix Uncachable TLB requests and decoding of xn bit | Gene Wu | |
| 2010-08-23 | ARM: For non-cachable accesses set the UNCACHABLE flag | Gene Wu | |
| 2010-08-23 | ARM: Implement DSB, DMB, ISB | Gene Wu | |
| 2010-08-23 | ARM: Get SCTLR TE bit from reset SCTLR | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX | Gene Wu | |
| 2010-08-23 | ARM: BX instruction can be contitional if last instruction in a IT block | Gene Wu | |
| Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. | |||
| 2010-08-23 | ARM: mark msr/mrs instructions as SerializeBefore/After | Min Kyu Jeong | |
| Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR | |||
| 2010-08-23 | ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. | Min Kyu Jeong | |
| THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false. | |||
| 2010-08-23 | ARM: adding genMachineCheckFault() stub for ARM that doesn't panic | Min Kyu Jeong | |
| 2010-08-23 | ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵ | Gene Wu | |
| ARMv7 | |||
| 2010-08-23 | ARM: Temporary local variables can't conflict with isa parser operands. | Gene Wu | |
| PC is an operand, so we can't have a temp called PC | |||
| 2010-08-23 | ARM: Exclusive accesses must be double word aligned | Ali Saidi | |
| 2010-08-23 | ARM: Add some registers for big loads/stores to support neon. | Ali Saidi | |
| 2010-08-23 | ARM: Decode neon memory instructions. | Ali Saidi | |
| 2010-08-23 | ARM: Clean up the ISA desc portion of the ARM memory instructions. | Gabe Black | |
| 2010-08-23 | ARM: We don't currently support ThumbEE exceptions, so don't report that we do | Ali Saidi | |
| 2010-08-23 | ARM: Add system for ARM/Linux and bootstrapping | Ali Saidi | |
| 2010-08-23 | ARM: Implement some more misc registers | Ali Saidi | |
| 2010-08-23 | ARM: Fix an un-initialized variable bug | Ali Saidi | |
| 2010-08-23 | Loader: Make the load address mask be a parameter of the system rather than ↵ | Ali Saidi | |
| a constant. This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0. | |||
| 2010-08-23 | ARM: Finish the timing translation when taking a fault. | Min Kyu Jeong | |
| 2010-08-23 | ARM: Use a stl queue for the table walker state | Dam Sunwoo | |
| 2010-08-23 | Compiler: Fixes for GCC 4.5. | Ali Saidi | |
| 2010-08-22 | X86: Get rid of unused file arguments.hh. | Gabe Black | |
| 2010-08-22 | SPARC: Fix some style issues in utility.hh. | Gabe Black | |
| 2010-08-22 | X86: Get rid of the unused getAllocator on the python base microop class. | Gabe Black | |
| This function is always overridden, and doesn't actually have the right signature. | |||
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