| Age | Commit message (Expand) | Author |
|---|
| 2017-11-22 | sparc: Return debug faults from unimplemented instructions. | Gabe Black |
| 2017-11-22 | sparc: Pull the unimplemented formats out of the ISA description. | Gabe Black |
| 2017-11-22 | sparc: Pull the "Uknown" StaticInst class out of the ISA description. | Gabe Black |
| 2017-11-22 | sparc: Pull most of the Nop format out of the ISA description. | Gabe Black |
| 2017-11-22 | sparc: Pull more StaticInst base classes out of the ISA desc. | Gabe Black |
| 2017-11-22 | sparc: Pull flat static instruction classes out of the ISA. | Gabe Black |
| 2017-11-21 | arch-arm: ArmPMU refactor | Jose Marinho |
| 2017-11-21 | arch-arm: Do not increment PMU cycle event in WFI/WFE | Jose Marinho |
| 2017-11-21 | arch-arm: Fix MCR/MRC disassemble | Giacomo Travaglini |
| 2017-11-21 | arch-arm: Fix MSR/MRS disassemble | Giacomo Travaglini |
| 2017-11-20 | arch-arm: Ensure counters keep events on checkpoint resume | Jose Marinho |
| 2017-11-20 | sparc: Pull StaticInst base classes out of the ISA description. | Gabe Black |
| 2017-11-17 | sim: Implement load_addr_mask auto-calculation | Geoffrey Blake |
| 2017-11-16 | arch, arm: Print value being ignored on DummyISA write | Sean McGoogan |
| 2017-11-15 | arch-arm: Dsb instruction shouldn't flush the pipeline | Giacomo Travaglini |
| 2017-11-15 | arch-arm: Writes to DCCMVAC shouldn't flush pipeline | Giacomo Travaglini |
| 2017-11-15 | arch-arm: Removing FlushPipe fault, using SquashAfter | Giacomo Travaglini |
| 2017-11-15 | arm: Add support for armv8 CRC32 instructions | Giacomo Travaglini |
| 2017-11-13 | arch-arm: Interface for the ArmStaticInst intWidth field | Giacomo Travaglini |
| 2017-11-13 | arch-arm: Corrected encoding for T32 HVC instruction | Giacomo Travaglini |
| 2017-11-10 | scons: Move Transform and termcap functionality into their own files. | Gabe Black |
| 2017-11-09 | arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1 | Nikos Nikoleris |
| 2017-11-07 | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates. | Gabe Black |
| 2017-11-02 | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts. | Gabe Black |
| 2017-10-31 | x86: Fix VEX instruction decoding. | Gabe Black |
| 2017-10-20 | arch-arm: RBIT instruction using mirroring func | Giacomo Travaglini |
| 2017-10-17 | scons: Stop generating inc.d in the isa parser. | Gabe Black |
| 2017-10-17 | arch-arm: Fix inverted 32/64-bit check in GDB | Boris Shingarov |
| 2017-10-13 | arch-arm: Signal an event when executing store exclusives | Nikos Nikoleris |
| 2017-10-13 | mem: Signal the local monitor when clearing the global monitor | Nikos Nikoleris |
| 2017-09-27 | arch-x86: fix CondInst decoding for MOV to Control Registers | Bjoern A. Zeeb |
| 2017-09-27 | arch: change panic for Vector traceData to warn_once | Bjoern A. Zeeb |
| 2017-09-21 | alpha: Move some initialization logic from loadState into unserialize. | Gabe Black |
| 2017-09-20 | kvm: arm: Get rid of functions which just wrap the subclasses version. | Gabe Black |
| 2017-09-11 | stats: Move the swpipl function into the Alpha kernel stats. | Gabe Black |
| 2017-09-11 | stats: Get rid of some kernel stats related cruft. | Gabe Black |
| 2017-08-30 | arch-arm: Only increment SW PMU counters on writes to PMSWINC | Jose Marinho |
| 2017-08-30 | arch-arm: Add missing override keywords in fault.hh | Andreas Sandberg |
| 2017-08-30 | arch-x86: Add missing override in the X86 TLB | Andreas Sandberg |
| 2017-08-30 | arch-sparc: Add a FaultVals instantiation for VecDisabled | Andreas Sandberg |
| 2017-08-30 | arch-alpha: Add missing overrides | Andreas Sandberg |
| 2017-08-28 | x86: Use the new CondInst format for moves to/from control registers. | Gabe Black |
| 2017-08-28 | x86: Add a "CondInst" format for conditionally decoded instructions. | Gabe Black |
| 2017-08-01 | arch-arm: Use named constants for m5op instructions | Andreas Sandberg |
| 2017-08-01 | kvm, arm: Switch to the device EQ when accessing ISA devices | Andreas Sandberg |
| 2017-08-01 | arch-arm: Switch to DTOnly as the default machine type | Andreas Sandberg |
| 2017-07-17 | sim, x86: Make clone a virtual function | Sean Wilson |
| 2017-07-17 | x86: Add stats to X86 TLB | Swapnil Haria |
| 2017-07-17 | riscv: Define register index constants using literals | Alec Roelke |
| 2017-07-14 | riscv: Disambiguate between the C and C++ versions of isnan and isinf. | Gabe Black |
