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2010-05-14SPARC: Implement the version of movcc that uses the fp condition codes.Gabe Black
2010-05-12X86: Make the cvti2f microop sign extend its integer source correctly.Gabe Black
The code was using the wrong bit as the sign bit. Other similar bits of code seem to be correct.
2010-05-12X86: Actual change that fixes div. How did that happen?Gabe Black
2010-05-03X86: Update the base aux vector X86 processes install.Gabe Black
2010-05-02X86: Sometimes CPUID depends on ecx, so pass that in.Gabe Black
2010-05-02X86: Finally fix a division corner case.Gabe Black
When doing an unsigned 64 bit division with a divisor that has its most significant bit set, the division code would spill a bit off of the end of a uint64_t trying to shift the dividend into position. This change adds code that handles that case specially by purposefully letting it spill and then going ahead assuming there was a 65th one bit.
2010-04-15tick: rename Clock namespace to SimClockNathan Binkert
2010-03-23cpu: fix exec tracing memory corruption bugSteve Reinhardt
Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes.
2010-03-10scons: import ply to work around scons sys.path weirdnessNathan Binkert
2010-02-26cpu_models: get rid of cpu_models.py and move the stuff into SConsNathan Binkert
2010-02-26isa_parser: Make SCons import the isa_parserNathan Binkert
this is instead of forking a new interpreter
2010-02-26isa_parser: move the operand map stuff into the ISAParser class.Nathan Binkert
2010-02-26isa_parser: move more support functions into the ISAParser classNathan Binkert
2010-02-26isa_parser: move more stuff into the ISAParser classNathan Binkert
2010-02-26isa_parser: move the formatMap and exportContext into the ISAParser classNathan Binkert
2010-02-26isa_parser: Make stack objects class members instead of globalsNathan Binkert
2010-02-26isa_parser: add a debug variable that changes how errors are reported.Nathan Binkert
This allows us to get tracebacks in certain cases where they're more useful than our error message.
2010-02-26isa_parser: Use an exception to flag errorNathan Binkert
This allows the error to propagate more easily
2010-02-26isa_parser: Move more stuff into the ISAParser classNathan Binkert
2010-02-26isa_parser: move code around to prepare for putting more stuff in the classNathan Binkert
2010-02-26isa_parser: simple fixes, formatting and styleNathan Binkert
2010-02-12O3PCU: Split loads and stores that cross cache line boundaries.Timothy M. Jones
When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.
2010-02-12Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.Timothy M. Jones
2009-11-05compile: compile on 32 bit hardwareNathan Binkert
2009-11-05isa_parser: allow negative integer literalsNathan Binkert
2010-01-19util: do checkpoint aggregation more cleanly, fix last changeset.Lisa Hsu
1) Move alpha-specific code out of page_table.cc:serialize(). 2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up. 3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN. 4) Fix the memory unserialize that I forgot somehow in the last changeset. 5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py. Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
2009-12-31MIPS: Beef up process initialization.Matt DeVuyst
2009-12-31MIPS: Implement the SE mode version of rdhwr.Gabe Black
2009-12-31MIPS: Fix decoding of the rdhwr instruction.Gabe Black
2009-12-31MIPS: Implement the set_thread_area system call.Gabe Black
2009-12-31MIPS: Create an artificial control register to hold the thread pointer.Gabe Black
In Linux, the set_thread_area system call stores the address of the thread local storage area into a field of the current thread_info structure. Later, to access that value, the program uses the rdhwr instruction to read a "hardware register" with index 29. The 64 bit MIPS manual, volume II, says that index 29 is reserved for a future ABI extension and should cause a "Reserved Instruction Exception". In Linux (and potentially other ISAs) that exception is trapped and emulated to return the value stored by set_thread_area as if that were actually stored by a physical register. The tp_value address (as named in the Linux kernel) is ironically stored as a control register so that it goes with a particular ThreadContext. Syscall emulation will use that to emulate storing to the OS's thread info structure, and rdhwr will emulate faulting and returning that value from software by returning the value itself, as if it was in hardware. In other words, we fake faking the register in SE mode. In an FS mode implementation it should work as specified in the manual.
2009-12-31MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.Gabe Black
The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.
2009-12-21MIPS: Add missing syscall slots.Gabe Black
These are all after the existing ones, suggesting they were added after the original list was created.
2009-12-20Alpha: Implement MVI and remaining BWX instructions.Soumyaroop Roy
2009-12-19X86: Add a common named flag for signed media operations.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate high multiplies.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate scalar media instructions.Gabe Black
2009-11-17ARM: Begin implementing CP15Ali Saidi
2009-11-17ARM: Differentiate between LDM exception return and LDM user regs.Ali Saidi
2009-11-17ARM: Boilerplate full-system code.Ali Saidi
--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-16imported patch isa_fixes2.diffAli Saidi
2009-11-15ARM: Make the exception return form of ldm restore CPSR.Gabe Black
2009-11-15ARM: Create a new type of load uop that restores spsr into cpsr.Gabe Black
2009-11-14ARM: Check in the actual change from the last commit.Gabe Black
The last commit was somehow empty. This was what was supposed to go in it.
2009-11-14ARM: Fix up the implmentation of the msr instruction.Gabe Black
2009-11-14ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.Gabe Black
2009-11-14ARM: Add a bitfield to indicate if an immediate should be used.Gabe Black
2009-11-14ARM: Write some functions to write to the CPSR and SPSR for instructions.Gabe Black
2009-11-14ARM: Fix up the implmentation of the mrs instruction.Gabe Black
2009-11-14ARM: More accurately describe the effects of using the control operands.Gabe Black