gem5 - gem5

Age	Commit message (Expand)	Author
2012-09-25	arm: Use a static_assert to test that miscRegName[] is complete	Andreas Sandberg
2012-09-25	ARM: Inst writing to cntrlReg registers not set as control inst	Nathanael Premillieu
2012-09-25	ARM: Predict target of more instructions that modify PC.	Ali Saidi
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-11	X86: make use of register predication	Nilay Vaish
2012-09-11	x86: Add a separate register for D flag bit	Nilay Vaish
2012-06-03	ISA Parser: Allow predication of source and destination registers	Nilay Vaish
2012-09-10	NetBSD: Build on NetBSD	Palle Lyckegaard
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-21	Device: Remove overloaded pio_latency parameter	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-08-16	Alpha System: override startup(), instead of loadState()	Nilay Vaish
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-08-15	sysemul: bump all linux versions of for syscal emulation to 3.0.	Ali Saidi
2012-08-06	syscall emulation: Enabled getrlimit and getrusage for x86.	Marc Orr
2012-08-06	syscall emulation: Clean up ioctl handling, and implement for x86.	Marc Orr
2012-07-27	ARM: fix value of MISCREG_CTR returned by readMiscReg()	Anthony Gutierrez
2012-07-22	X86 CPUID: Return false if unknown processor family	Nilay Vaish
2012-07-11	x86: added page size in bytes tlb entry function	Brad Beckmann
2012-07-10	syscall emulation: Add the futex system call.	Marc Orr
2012-07-10	x86: logSize and lruSeq are now optional ckpt params	Brad Beckmann
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-07-02	gcc: Fix warnings for gcc 4.7 and clang 3.1	Andreas Hansson
2012-06-29	ARM: Fix identification of one RAS pop instruction.	Ali Saidi
2012-06-29	ARM: Update version of linux we claim to be to 3.0.0.	Ali Saidi
2012-06-29	ARM: Fix issue with predicted next pc being wrong because of advance() ordering.	Ali Saidi
2012-06-11	ARM: implement the ProcessInfo methods	Anthony Gutierrez
2012-06-08	Power: Fix MaxMiscDestRegs which was set to zero	Andreas Hansson
2012-06-07	X86 TLB: Add a missing = sign	Nilay Vaish
2012-06-07	X86 TLB: Fix for gcc 4.4.3	Jayneel Gandhi
2012-06-05	cpu: Don't init simple and inorder CPUs if they are defered.	Anthony Gutierrez
2012-06-05	ISA: Back-out NoopMachInst as a StaticInstPtr change.	Ali Saidi
2012-06-05	ARM: removed extra white space	Chander Sudanthi
2012-06-05	ARM: Fix MPIDR and MIDR register implementation.	Chander Sudanthi
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-06-05	ARM: Fix compilation on ARM after Gabe's change.	Ali Saidi
2012-06-04	ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.	Gabe Black
2012-06-04	X86: Ensure that the CPUID instruction always writes its outputs.	Gabe Black
2012-06-04	X86: Ensure that the decoder's internal ExtMachInst is completely initialized.	Gabe Black
2012-05-28	X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.	Gabe Black
2012-05-27	X86: Move the GDT down to where it can be accessed in 32 bit mode.	Gabe Black
2012-05-27	X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.	Gabe Black
2012-05-26	ISA,CPU: Generalize and split out the components of the decode cache.	Gabe Black
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-05-23	DMA: Split the DMA device and IO device into seperate files	Andreas Hansson