gem5 - gem5

Age	Commit message (Expand)	Author
2011-09-19	SPARC: Remove #if FULL_SYSTEMs from the ISA description.	Gabe Black
2011-09-19	MIPS: Get rid of #if style config checks in the ISA description.	Gabe Black
2011-09-19	MIPS: Guard SystemCallFault::invoke consistently.	Gabe Black
2011-09-19	MIPS: Get rid of the unused (and partially defined) CacheError fault.	Gabe Black
2011-09-19	Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.	Gabe Black
2011-09-19	X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.	Gabe Black
2011-09-19	PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.	Gabe Black
2011-09-18	Pseudoinst: Add an initParam pseudo inst function.	Gabe Black
2011-09-13	ARM: update TLB to set request packet ASID field	Daniel Johnson
2011-09-13	CP15 c15: enable execution with accesses to c15 registers	Chander Sudanthi
2011-09-13	ARM: Implement numcpus bits in L2CTLR register.	Daniel Johnson
2011-09-13	LSQ: Only trigger a memory violation with a load/load if the value changes.	Ali Saidi
2011-09-10	MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.	Deyuan Guo
2011-09-09	StaticInst: Merge StaticInst and StaticInstBase.	Gabe Black
2011-09-09	Decode: Pull instruction decoding out of the StaticInst class into its own.	Gabe Black
2011-09-09	Stack: Tidy up some comments, a warning, and make stack extension consistent.	Gabe Black
2011-09-08	ISA parser: Don't look for operands in strings.	Gabe Black
2011-09-08	ISA parser: Match /* */ and // style comments.	Gabe Black
2011-09-05	X86: Make sure instruction flags are set properly even on 32 bit machines.	Gabe Black
2011-09-05	X86,TLB: Make sure the "delayedResponse" variable is always set.	Gabe Black
2011-09-02	TLB: comments and a helpful warning.	Lisa Hsu
2011-08-19	ARM: Mark some variables uncacheable until boot all CPUs are enabled.	Ali Saidi
2011-08-19	ARM: Add VExpress_E support with PCIe to gem5	Ali Saidi
2011-08-19	ARM: Add support for Versatile Express boards	Ali Saidi
2011-08-19	ARM: Add support for DIV/SDIV instructions.	Ali Saidi
2011-08-19	Fix bugs due to interaction between SEV instructions and O3 pipeline	Geoffrey Blake
2011-08-19	ARM: Fix a memory leak with the table walker.	Ali Saidi
2011-08-13	X86: Use IsSquashAfter if an instruction could affect fetch translation.	Gabe Black
2011-07-15	ARM: Fix SWP/SWPB undefined instruction behavior	Wade Walker
2011-07-15	ARM: Add two unimplemented miscellaneous registers.	Wade Walker
2011-07-11	X86: implements copyRegs() function	Nilay Vaish
2011-07-11	ISA: Get rid of the unused mem_acc_type template parameter.	Gabe Black
2011-07-07	alpha:hwrei:rollback for o3	Korey Sewell
2011-07-05	grammar: better encapsulation of a grammar and parsing	Nathan Binkert
2011-07-05	ISAs: Streamline some spots where Mem is used in the ISA descriptions.	Gabe Black
2011-07-05	ISA parser: Define operand types with a ctype directly.	Gabe Black
2011-07-05	ISA parser: Simplify operand type handling.	Gabe Black
2011-07-02	ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.	Gabe Black
2011-07-02	ISA: Use readBytes/writeBytes for all instruction level memory operations.	Gabe Black
2011-07-02	X86: Fix store microops so they don't drop faults in timing mode.	Gabe Black
2011-06-28	arch: print next upc correctly	Nilay Vaish
2011-06-22	mips: fix nmsub and nmadd definitions	Deyaun Guo
2011-06-21	X86: Eliminate an unused argument for building store microops.	Gabe Black
2011-06-19	mips: mark unaligned access flag as true	Korey Sewell
2011-06-19	inorder/dtb: make sure DTB translate correct address	Korey Sewell
2011-06-19	alpha: fix warn_once for prefetches	Korey Sewell
2011-06-19	alpha: naming for dtb faults	Korey Sewell
2011-06-19	alpha: make hwrei a control inst	Korey Sewell
2011-06-19	sparc: init. cache state in TLB	Korey Sewell
2011-06-19	cpus/isa: add a != operator for pcstate	Korey Sewell