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2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
2017-07-05arm,kvm: update CP15 timer model when exiting KvmCurtis Dunham
The ARM MiscRegs implementation has two interfaces: 'normal' and 'no effect'. The latter acts as a way to access the backing store without architectural 'effects'. For instance, a normal write to a timer compare value would call into the timer model to emulate the device. The 'no effect' interface, however, would just write the value into the register backing store and do nothing else. For Kvm execution, a delicate balance must be struck for the timer device specifically. We need the code in the model to be run, because it contains state other than the register backing store that must stay in sync. On the other hand, we don't necessarily want the timer model to schedule gem5 events when this happens. In this commit, we ensure that we use the 'effectful' MiscReg interface when copying the CP15 timer registers from Kvm back into gem5. The prior commit makes sure that this doesn't generate unnecessary timer events or interrupts. Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9 Reviewed-on: https://gem5-review.googlesource.com/3543 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05kvm: move Kvm check from ARM Kvm GIC to SystemCurtis Dunham
The check was nearly completely generic anyway, with the exception of the Kvm CPU type. This will make it easier for other parts of the codebase to do similar checks. Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da Reviewed-on: https://gem5-review.googlesource.com/3540 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-22arm,sim: fix context switch stats dumps for ARM64/LinuxPaul Rosenfeld
32bit and 64bit Linux have different arguments passed to the __switch_to() function that gem5 hooks into in order to collect context switch statistics. 64bit Linux provides the task_struct pointer to the next task that will be switched to, which means we don't have to look up the task_struct from thread_info as we do in 32bit ARM Linux. This patch adds a second set of accessors to ThreadInfo to extract details such as the pid, tgid, task name, etc., directly from a task_struct. The existing accessors maintain their existing behavior by first looking up the task_struct and then calling these new accessors. A 64-bit variant of the DumpStatsPCEvent class is added that uses these new accessors to get the task details for the context switch dumps directly from the task_struct passed to __switch_to(). Change-Id: I63c4b3e1ad64446751a91f6340901d5180d7382d Reviewed-on: https://gem5-review.googlesource.com/2640 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-20sim, x86: Replace EventWrapper use with EventFunctionWrapperSean Wilson
Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3749 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-06-20arm: Replace EventWrapper use with EventFunctionWrapperSean Wilson
Change-Id: I08de5f72513645d1fe92bde99fa205dde897e951 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3747 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-15x86: Add consistent overrides to process.hhSean Wilson
Change-Id: I912601b6f781a0bbedd06583c059589374f6d5c6 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3720 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Joe Gross <joe.gross@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-15x86: Fixed remote debugging of simulated codeMatthias Hille
GDB breaks if more bytes are sent than the transmitted registers actually need. Therefore the GdbRegCache struct needs to be packed to prevent padding at the end. Change-Id: Ib2c14eb70becdac609eb4f475d5dddbd5bcc60da Signed-off-by: Matthias Hille <matthiashille8@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/3020 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-26x86: Rework how VEX prefixes are decoded.Gabe Black
Remove redundant information from the ExtMachInst, hash the vex information to ensure the decode cache works properly, print the vex info when printing an ExtMachInst, consider the vex info when comparing two ExtMachInsts, fold the info from the vex prefixes into existing settings, remove redundant decode code, handle vex prefixes one byte at a time and don't bother building up the entire prefix, and let instructions that care about vex use it in their implementation, instead of developing an entire parallel decode tree. This also eliminates the error prone vex immediate decode table which was incomplete and would result in an out of bounds access for incorrectly encoded instructions or when the CPU was mispeculating, as it was (as far as I can tell) redundant with the tables that already existed for two and three byte opcodes. There were differences, but I think those may have been mistakes based on the documentation I found. Also, in 32 bit mode, the VEX prefixes might actually be LDS or LES instructions which are still legal in that mode. A valid VEX prefix would look like an LDS/LES with an otherwise invalid modrm encoding, so use that as a signal to abort processing the VEX and turn the instruction into an LES/LDS as appropriate. Change-Id: Icb367eaaa35590692df1c98862f315da4c139f5c Reviewed-on: https://gem5-review.googlesource.com/3501 Reviewed-by: Joe Gross <joe.gross@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-05-25x86: sim: Make 32 bit x86 processes work again.Gabe Black
When the LiveProcess class was renamed to be just Process, the CL author also changed the syscall function from a virtual function into a regular one. Unfortunately, the I386Process class overrode the syscall function to adjust the return address so that control would return to the right place. Without that adjustment, 32 bit x86 process would segfault and die immediately after their first system call. This change reinstates the virtual specifier on the base syscall function, and adds an override keyword on the I386Process's version so that it won't be orphaned again in the future. It also fixes some small style issues the style checker script complained about. Change-Id: I0d1178ea0eda6676050c8fc043820a2bb4d99c0d Reviewed-on: https://gem5-review.googlesource.com/3500 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-24arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMUAndreas Sandberg
The PMU model currently doesn't calculate the PMU event counter index correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this obvious mistake. Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3121 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-05-23arch-riscv: Fix bad stack initializationAlec Roelke
This patch fixes a problem with RISC-V initial stack setup in SE mode where the AT_RANDOM aux vector value contains an address that is too close to the top of the stack and doesn't fit the required 16 bytes. To fix this, the program header table was added to the top of the stack just like the RISC-V proxy kernel does. Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3 Reviewed-on: https://gem5-review.googlesource.com/3401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-05-23arch-arm: Fix some poorly done type max and min in NEONRekai Gonzalez-Alberquilla
The ISA code for ARM calculates min and max elements for types using bit manipulation. That triggers some warnings, treated as errors, as the compiler can tell that there is an overflow and the sign flips. Fixed using standard lib definitions instead. Change-Id: Ie2331b410c7f76d4bd87da5afe9edf20c8ac91b3 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3481 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-19base, sim, arch: Fix clang 5.0 warningsAndreas Sandberg
Compiling gem5 with recent version of clang (4 and 5) triggers warnings that are treated as errors: * Global templatized static functions result in a warning if they are not used. These should either be declared as static inline or without the static identifier to avoid the warning. * Some templatized classes contain static variables. The instantiated versions of these variables / templates need to be explicitly declared to avoid a compiler warning. Change-Id: Ie8261144836e94ebab7ea04ccccb90927672c257 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3420 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-18base: Refactor the GDB code.Gabe Black
The new version modularizes the implementation of the various commands, gets rid of dynamic allocation of the register cache, fixes some small style problems, and uses exceptions to simplify error handling internal to the GDB stub. Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2 Reviewed-on: https://gem5-review.googlesource.com/3280 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Boris Shingarov <shingarov@gmail.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-18syscall_emul, riscv: add override keyword to RISCV Process classBrandon Potter
Change-Id: I2a146ae57aac3787389997961208474a97e7c155 Reviewed-on: https://gem5-review.googlesource.com/3360 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-05-16x86: Fix the multiplication microops.Gabe Black
If the operands were 64 bit, an intermediate calculation could lose a carry bit. This change rearranges that intermediate calculation if the operand width is large, and reworks the microop implementation in general in an attempt to make it easier to understand. Change-Id: Ib36333f3f2695a33cd9623e43682de22ebd2e7ea Reviewed-on: https://gem5-review.googlesource.com/3381 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-05-12arm: Remove unused DumpStatsPCEventF class in FreeBSD systemAndreas Sandberg
The DumpStatsPCEventF is declared but lacks an implementation. This confuses RTTI in clang. Remove this class since it is clearly not needed. Change-Id: Ib95f09f2ba8593f8d0e072b96afd5f8a9ed31070 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3240 Reviewed-by: B.A. Zeeb <baz21@cam.ac.uk>
2017-05-10scons: Use the generalized switching headers on the GPU ISA.Gabe Black
Now that the switching header implementation has been generalized, there's no need to have two nearly identical implementations for the two different groups of headers. Change-Id: Ie7c24fcddbc672ac5ca2d69bfc35696f42c55580 Reviewed-on: https://gem5-review.googlesource.com/2984 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-10scons: arch: Generalize the switching header code.Gabe Black
Factor out the ISA ness of the switching header generating function. Also turn it into a SCons builder which builds a single header, and a wrapping method which uses the builder on a group of header files which all target the same subdirectory. Change-Id: I87705f97b6ebd9baebd4ebcfea19cc1218a64ad0 Reviewed-on: https://gem5-review.googlesource.com/2983 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-09arm: Add support for memory-mapped m5opsAndreas Sandberg
Add support for a memory mapped m5op interface. When enabled, the TLB intercepts accesses in the 64KiB region designated by the ArmTLB.m5ops_base parameter. An access to this range maps to a specific m5op call. The upper 8 bits of the offset into the range denote the m5op function to call and the lower 8 bits denote the subfunction. Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2964
2017-05-09kvm, arm: Fix incorrect PSTATE syncAndreas Sandberg
The state transfer code wasn't reading back PSTATE correctly from the CPU prior to updating the thread context and was incorreclty writing the register as a 32-bit value when updating KVM. Correctly read back the state before updating gem5's view of PSTATE and cast the value to a uint64_t. Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2963 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
Use the PyBind11 wrapping infrastructure instead of SWIG to generate wrappers for functionality that needs to be exported to Python. This has several benefits: * PyBind11 can be redistributed with gem5, which means that we have full control of the version used. This avoid a large number of hard-to-debug SWIG issues we have seen in the past. * PyBind11 doesn't rely on a custom C++ parser, instead it relies on wrappers being explicitly declared in C++. The leads to slightly more boiler-plate code in manually created wrappers, but doesn't doesn't increase the overall code size. A big benefit is that this avoids strange compilation errors when SWIG doesn't understand modern language features. * Unlike SWIG, there is no risk that the wrapper code incorporates incorrect type casts (this has happened on numerous occasions in the past) since these will result in compile-time errors. As a part of this change, the mechanism to define exported methods has been redesigned slightly. New methods can be exported either by declaring them in the SimObject declaration and decorating them with the cxxMethod decorator or by adding an instance of PyBindMethod/PyBindProperty to the cxx_exports class variable. The decorator has the added benefit of making it possible to add a docstring and naming the method's parameters. The new wrappers have the following known issues: * Global events can't be memory managed correctly. This was the case in SWIG as well. Change-Id: I88c5a95b6cf6c32fa9e1ad31dfc08b2e8199a763 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Andrew Bardsley <andrew.bardsley@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2231 Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-01arch-sparc: Fix wrong indentation causing warnings for gcc 6Nikos Nikoleris
Change-Id: I94e15ae79f0e73692d882f62fd2b7bf45cf0c841 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2900 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-18x86: fixed branching() computation for branch uopsSanti Galan
When a branch micro-op belongs to a flow and the micro-op does not change the nPC and just updates the nuPC (like a 'rep movs' flow), branching() function always returns not-taken no matter actual micro-branch outcome. Provided fix adds to the equation nuPC attribute checking since these kind of branch micro-op only updates that pointer. This issue has been found while debugging the performance of a copy-loop implemented with memcopy function. Without the fix, 'rep movss' internal micro-branch was always predicted as not-taken causing an squash event after every branch micro-branch execution. Using the provided test, branch mispredition went from 1922 without the fix to 7. Change-Id: I1bcbefae26aef47e3135817ef99b53d0ea0a98fa
2017-04-11riscv: Fix crashes with large or frequent mmapsAlec Roelke
This patch fixes a bug where increasing the mmap region too much causes it to run into already-allocated memory, which causes gem5 to fail an assertion. Previously, the stack was incorrectly set up such that the end of the mmap region and the top of the stack were the same address and both would grow downward. With this patch, the top of the stack has been separated from the end of mmap and moved up, and the mmap region now grows upward instead of downward. [Rebase to master branch and remove dependencies.] Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520 Reviewed-on: https://gem5-review.googlesource.com/2680 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
Some of the functions in the Linux toolchain that allocate memory make use of paired LR and SC instructions, which didn't work properly for that toolchain. This patch fixes that so attempting to use those functions doesn't cause an endless loop of failed SC instructions. Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7 Reviewed-on: https://gem5-review.googlesource.com/2340 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix compatibility with Linux toolchainAlec Roelke
Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain (riscv64-unknown-elf-*) due to incorrect assumptions made in the initial setup of the user stack in SE mode. This patch fixes that by referring to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and setting up the stack according to how it does it. Now binaries compiled using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as well. [Update for recent changes to MemState to add accessors and mutators to get its members.] Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285 Reviewed-on: https://gem5-review.googlesource.com/2305 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: add remote gdb supportAlec Roelke
This patch adds support for debugging with remote GDB to RISC-V. Using GDB compiled with the RISC-V GNU toolchain, it is possible to pause and continue execution, view debugging information, etc. As with the rest of RISC-V, this does not support full-system mode. Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d Reviewed-on: https://gem5-review.googlesource.com/2304 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix error on memory op address overflowAlec Roelke
Previously, if a memory operation referenced an address that caused the data to wrap around to the beginning of the memory (such as -1 or 0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and gem5 would crash. This patch fixes that by checking for such a case in RISC-V's TLB code and returning a fault from translateData if that would happen. Because RISC-V does support unaligned memory accesses, no checking is performed to make sure that an access doesn't cross a cache line. [Update creation of page table fault to use make_shared.] [Add comment explaining the change and assertion that the memory request isn't zero size.] Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410 Reviewed-on: https://gem5-review.googlesource.com/2345 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: enable unaligned memory accessesAlec Roelke
Sometimes an ld instruction will be split across a cache boundary. Previously RISC-V was set to not allow this. This patch fixes that. Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f Reviewed-on: https://gem5-review.googlesource.com/2341 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03arm, kvm: implement GIC state transferCurtis Dunham
This also allows checkpointing of a Kvm GIC via the Pl390 model. Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2444 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: Don't panic when checking coprocessor read/write permissionsNikos Nikoleris
Instructions that use the coprocessor interface check the current program status to determine whether the current context has the priviledges to read from/write to the coprocessor. Some modes allow the execution of coprocessor instructions, some others do not allow it, while some other modes are unexpected (e.g., executing an AArch32 instruction while being in an AArch64 mode). Previously we would unconditionally trigger a panic if we were in an unexpected mode. This change removes the panic and replaces it with an Undefined Instruction fault that triggers if and when a coprocessor instruction commits in an unexpected mode. This allows speculative coprocessor instructions from unexpected modes to execute but prevents them from gettting committed. Change-Id: If2776d5bae2471cdbaf76d0e1ae655f501bfbf01 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2281 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: Treat Write-Through Normal memory as Non-CacheableNikos Nikoleris
A completed write to a memory location that is Write-Through Cacheable has to be visible to an external observer without the need of explicit cache maintenance. This change adds support for Write-Through Cacheable Normal memory and treats it as Non-cacheable. This incurs a small penalty as accesses to the memory do not fill in the cache but does not violate the properties of the memory type. Change-Id: Iee17ef9d952a550be9ad660b1e60e9f6c4ef2c2d Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2280 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03arm, kvm: Override the kernel's default MPIDR valueAndreas Sandberg
The kernel and gem5 derive MPIDR values from CPU IDs in slightly different ways. This means that guests running in a multi-CPU setup sometimes fail to bring up secondary CPUs. Fix this by overriding the MPIDR value in virtual CPUs just after they have been instantiated. Change-Id: I916d44978a9c855ab89c80a083af45b0cea6edac Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2461 Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: fix template instantiation warning in clangMatteo Andreozzi
In arch/arm/faults.hh, template the static member vals require explicit specialisation to avoid compiler warnings. Change-Id: Ie404ccaa43269cb1bb819e33153e776abbf3a79b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-09syscall-emul: Ignore unimplemented system callsBrandon Potter
This changeset sets the implementation policy for a subset of system calls to the ignoreFunc implementation (for x86 only). The ignored system calls likely will never be implemented and this allows a warning to be issued instead of the simulation exiting with a fatal. Change-Id: I8d9741ad683151e88cc71156d3602e2d0ccb0acf Reviewed-on: https://gem5-review.googlesource.com/2270 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Rewrite system call exit codeBrandon Potter
The changeset does a major refactor on the exit, exit_group, and futex system calls regarding exit functionality. A FutexMap class and related structures are added into a new file. This increases code clarity by encapsulating the futex operations and the futex state into an object. Several exit conditions were added to allow the simulator to end processes under certain conditions. Also, the simulation only exits now when all processes have finished executing. Change-Id: I1ee244caa9b5586fe7375e5b9b50fd3959b9655e Reviewed-on: https://gem5-review.googlesource.com/2269 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Add the tgkill system callBrandon Potter
This changeset adds support to kill a thread group by calling the tgkill system call. The functionality is needed in some pthread applications. Change-Id: I0413a3331be69b74dfab30de95384113ec4efb63 Reviewed-on: https://gem5-review.googlesource.com/2268 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
2017-03-09syscall-emul: Add or extend dup, dup2, and pipeBrandon Potter
This changeset extends the pipe system call to work with architectures other than Alpha (and enables the syscall for x86). For the dup system call, it sets the clone-on-exec flag by default. For the dup2 system call, the changeset adds an implementation (and enables it for x86). Change-Id: I00ddb416744ee7dd61a5cd02c4c3d97f30543878 Reviewed-on: https://gem5-review.googlesource.com/2266 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
2017-03-09syscall-emul: Add functionality to open syscallsBrandon Potter
This changeset adds refactors the existing open system call, adds the openat variant (enabled for x86 builds), and adds additional "special file" test cases for /proc/meminfo and /etc/passwd. Change-Id: I6f429db65bbf2a28ffa3fd12df518c2d0de49663 Reviewed-on: https://gem5-review.googlesource.com/2265 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
2017-03-09style: Correct some style issuesBrandon Potter
This changeset fixes line alignment issues, spacing, spelling, etc. for files that are used during SE Mode. Change-Id: Ie61b8d0eb4ebb5af554d72f1297808027833616e Reviewed-on: https://gem5-review.googlesource.com/2264 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
2017-03-09syscall-emul: Move memState into its own fileBrandon Potter
The Process class is full of implementation details and structures related to SE Mode. This changeset factors out an internal class from Process and moves it into a separate file. The purpose behind doing this is to clean up the code and make it a bit more modular. Change-Id: Ic6941a1657751e8d51d5b6b1dcc04f1195884280 Reviewed-on: https://gem5-review.googlesource.com/2263 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-03arm, kvm: enable running 32-bit Guest under ARM KVM64Rahul Thakur
1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit when running 32-bit OS 2) Correctly map 64-bit registers to banked 32-bit ones Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670 Reviewed-on: https://gem5-review.googlesource.com/2261 Maintainer: Rahul Thakur <rjthakur@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-03arm, kvm: fix saving/restoring conditional flags in ARM KVM64Rahul Thakur
The gem5 stores flags separately from other fields CPSR, so we need to split them out and recombine on trips to/from KVM. Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb Reviewed-on: https://gem5-review.googlesource.com/2260 Reviewed-by: Rahul Thakur <rjthakur@google.com> Maintainer: Rahul Thakur <rjthakur@google.com>
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess ↵Brandon Potter
simulations Modifies the clone system call and adds execve system call. Requires allowing processes to steal thread contexts from other processes in the same system object and the ability to detach pieces of process state (such as MemState) to allow dynamic sharing.
2017-02-27syscall_emul: [patch 14/22] adds identifier system callsBrandon Potter
This changeset add fields to the process object and adds the following three system calls: setpgid, gettid, getpid.
2017-02-27x86: remove unnecessary parameter from functionsBrandon Potter
2017-02-27gpu-compute: remove unnecessary member from classTony Gutierrez
The clang compiler complains that the wavefront member in the GpuISA class is unused. This changeset removes the member, because it does not appear serve a purpose.
2017-02-27gpu-compute: mark functions with override if replacing virtualBrandon Potter
The clang compiler is more stringent than the recent versions of GCC when dealing with overrides. This changeset adds the specifier to the methods which need it to silence the compiler.