Age | Commit message (Collapse) | Author | |
---|---|---|---|
2009-02-06 | Quell g++ 4.3 warning about operator ambiguity | Nathan Binkert | |
2009-02-01 | X86: All x86 fault classes now attempt to do something useful. | Gabe Black | |
2009-02-01 | X86: Make the fault classes handle error codes better. | Gabe Black | |
2009-02-01 | X86: Make the long mode interrupt/exception microcode handle an error code. | Gabe Black | |
2009-02-01 | X86: Distinguish between hardware and software interrupts/exceptions | Gabe Black | |
2009-02-01 | X86: Fix the upper bound on some ranges that were setting up the micro code ↵ | Gabe Black | |
assembler. | |||
2009-02-01 | X86: Make the chks microop check for the right int descriptor type. | Gabe Black | |
2009-02-01 | X86: Touch up the interrupt entering microcode. | Gabe Black | |
2009-02-01 | X86: Keep track of the vector for all exceptions/faults. | Gabe Black | |
2009-02-01 | X86: Fix the time keeping of the Local APIC timer. | Gabe Black | |
2009-02-01 | X86: Fix the microcode for the LODS instruction. | Gabe Black | |
2009-02-01 | X86: Fix some incorrect register widths. | Gabe Black | |
2009-02-01 | X86: Add extended Intel MP entries correctly. | Gabe Black | |
2009-02-01 | X86: Compute PCI config addresses correctly. | Gabe Black | |
2009-02-01 | X86: Calculate flags based on the actual result. | Gabe Black | |
2009-02-01 | X86: Set/correct some default values for x86 parameters. | Gabe Black | |
2009-01-30 | Errors: Use the correct panic/warn/fatal/info message in some places. | Ali Saidi | |
2009-01-25 | X86: Implement the xadd instruction. | Gabe Black | |
2009-01-25 | X86: Implement the bswap instruction. | Gabe Black | |
2009-01-25 | X86: Fix a bug in the iret microcode. | Gabe Black | |
2009-01-25 | X86: Make the interrupt object wake up the CPU when something becomes pending. | Gabe Black | |
2009-01-25 | CPU: Add a setCPU function to the interrupt objects. | Gabe Black | |
2009-01-24 | pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu. | Nathan Binkert | |
It's instantaneous and so it's somewhat bogus, but it's a first step. | |||
2009-01-19 | tracing: Add help strings for some of the trace flags | Nathan Binkert | |
2009-01-13 | SCons: centralize the Dir() workaround for newer versions of scons. | Nathan Binkert | |
Scons bug id: 2006 M5 Bug id: 308 | |||
2009-01-06 | X86: Hook in the M5 pseudo insts. | Gabe Black | |
2009-01-06 | X86: Autogenerate macroop generateDisassemble function. | Gabe Black | |
2009-01-06 | X86: Move the function that prints memory args into the inst base class. | Gabe Black | |
2009-01-06 | X86: Move the macroop class out of the isa description into C++. | Gabe Black | |
2009-01-06 | X86: Change indentation on microop disassembly. | Gabe Black | |
2008-12-17 | Make Alpha pseudo-insts available from SE mode. | Steve Reinhardt | |
2008-12-16 | SPARC: Truncate syscall args and return values appropriately. | Gabe Black | |
2008-12-07 | imported patch aux-fix.patch | Lisa Hsu | |
2008-12-06 | X86: Add add_entry back in. | Gabe Black | |
2008-12-06 | flags: Change naming of functions to be clearer | Nathan Binkert | |
2008-12-05 | This brings M5 closer to modernity - the kernel being advertised is newer so ↵ | Lisa Hsu | |
it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs. | |||
2008-12-04 | This patch pulls out the auxiliary vector struct from individual ISA | Lisa Hsu | |
LiveProcesses to the base LiveProcess definition so anyone can use them. | |||
2008-11-15 | syscalls: fix latent brk/obreak bug. | Steve Reinhardt | |
Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process. | |||
2008-11-14 | Fix a bunch of bugs I introduced when I changed the flags stuff for packets. | Nathan Binkert | |
I did some of the flags and assertions wrong. Thanks to Brad Beckmann for pointing this out. I should have run the opt regressions instead of the fast. I also screwed up some of the logical functions in the Flags class. | |||
2008-11-10 | pseudo inst: Add rpns (read processor nanoseconds) instruction. | Nathan Binkert | |
This instruction basically returns the number of nanoseconds that the CPU has been running. | |||
2008-11-10 | mem: update stuff for changes to Packet and Request | Nathan Binkert | |
2008-11-09 | X86: Fix completeAcc get call. | Gabe Black | |
2008-11-05 | Fix a few more places where the context stuff wasn't changed | Nathan Binkert | |
2008-11-04 | get rid of all instances of readTid() and getThreadNum(). Unify and eliminate | Lisa Hsu | |
redundancies with threadId() as their replacement. | |||
2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu | |
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. | |||
2008-11-02 | Make it so that all thread contexts are registered with the System, even in | Lisa Hsu | |
SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. | |||
2008-11-02 | make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered | Lisa Hsu | |
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. | |||
2008-10-21 | style: Use the correct m5 style for things relating to interrupts. | Nathan Binkert | |
2008-10-20 | O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. ↵ | Ali Saidi | |
Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change. | |||
2008-10-16 | get rid of local variable that's only used in an assert so fast compiles | Nathan Binkert | |