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AgeCommit message (Expand)Author
2008-07-01Change everything to use the cached virtPort rather than created their own ea...Ali Saidi
2008-06-14Fix various SWIG warningsNathan Binkert
2008-06-12X86: Make the cpuid processor identifier return a real string.Gabe Black
2008-06-12X86: Make the e820 table manually or automatically configurable from python.Gabe Black
2008-06-12X86: Make the disassembly for halt conform with the other microops.Gabe Black
2008-06-12X86: Implement and hook up STI and CLI instructions.Gabe Black
2008-06-12X86: Add an event for the apic timer timeout. It doesn't get used yet.Gabe Black
2008-06-12X86: Rename the divide count register to divide configuration.Gabe Black
2008-06-12X86: Make the apic isr and irr work.Gabe Black
2008-06-12X86: Make the apic task priority register work.Gabe Black
2008-06-12X86: Make the logical destination and destination format work.Gabe Black
2008-06-12X86: Make the apic ID register work.Gabe Black
2008-06-12X86: Make the apic version register work.Gabe Black
2008-06-12X86: Implement a partial, sort of correct version of the protected mode varia...Gabe Black
2008-06-12X86: Change how segment loading is performed.Gabe Black
2008-06-12X86: Make pushes and pops use the stack size instead of the data size.Gabe Black
2008-06-12X86: In non 64bit mode, throw a fault when a NULL segment is accessed.Gabe Black
2008-06-12X86: Take advantage of the new meta register.Gabe Black
2008-06-12X86: Keep handy values like the operating mode in one register.Gabe Black
2008-06-12X86: Change what the microop chks does.Gabe Black
2008-06-12X86: Add a microop to read a segments attribute register.Gabe Black
2008-06-12X86: Add microops and supporting code to manipulate the whole rflags register.Gabe Black
2008-06-12X86: Add microops which panic, fatal, warn, and warn_once.Gabe Black
2008-06-12X86: Truncate descriptors to 16 bits.Gabe Black
2008-06-12X86: Redo BSF.Gabe Black
2008-06-12X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate.Gabe Black
2008-06-12X86: Make string instructions work when rcx=0.Gabe Black
2008-06-12X86: Have all 8 machine check registers since the kernel assumes they're there.Gabe Black
2008-06-12X86: Bypass unaligned access support for register addressed MSRs.Gabe Black
2008-06-12X86: Remove enforcement of APIC register access alignment. Panic if more than...Gabe Black
2008-06-12X86: Fix the implementation of BSF.Gabe Black
2008-06-12X86: Bit scan forward/reverse were accidentally transposed.Gabe Black
2008-06-12X86: Fix a byte register indexing issue in the sign extending move from memor...Gabe Black
2008-06-12X86: Add in some support for the tsc register.Gabe Black
2008-06-11X86: Fix building on *BSD hostsAli Saidi
2008-06-11SCons: Fix more SCons version issuesAli Saidi
2008-05-20SCons: Fixing SCons bug 2006 issues for non-alpha ISAsStephen Hines
2008-03-25X86: Start implementing the south bridge stuff.Gabe Black
2008-03-06X86: Refine the local APIC.Gabe Black
2008-03-01X86: Don't map the local APIC into the physical address space in SE mode.Gabe Black
2008-02-26X86: Put in initial implementation of the local APIC.Gabe Black
2008-02-26X86: Implement the INVLPG instruction and the TIA microop.Gabe Black
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
2008-02-26X86: Get PCI config space to work, and adjust address space prefix numbering ...Gabe Black
2008-02-06Make the Event::description() a const functionStephen Hines
2008-02-05Add base ARM code to M5Stephen Hines
2008-01-23X86: Put an SMBios/DMI table in memory.Gabe Black
2008-01-23X86: Optomize the bit scanning instruction microassembly a little. More can b...Gabe Black
2008-01-22X86: Implement and attach the BSR and BSF instructions.Gabe Black
2008-01-21X86: Fill out group17 in the decoder.Gabe Black
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