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2016-09-16hsail: Fix disassembly of load instruction with 3 destination operandsAlexandru Dutu
2016-09-16gpu-compute: Refactoring Wavefront::dynWaveIdAlexandru Dutu
2016-09-16gpu-compute: Wavefront refactoringAlexandru Dutu
Renaming members of the Wavefront class in accordance with the style guide.
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
Change-Id: Id2acbc09772be310a0eb9e33295afab07e08a4fa Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-13x86: Force strict ordering for memory mapped m5opsMichael LeBeane
Normal MMAPPED_IPR requests are allowed to execute speculatively under the assumption that they have no side effects. The special case of m5ops that are treated like MMAPPED_IPR should not be allowed to execute speculatively, since they can have side-effects. Adding the STRICT_ORDER flag to these requests blocks execution until the associated instruction hits the ROB head.
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-05sim: fix issues with pwrite(); don't enable fstatfsTony Gutierrez
this patch fixes issues with changeset 11593 use the host's pwrite() syscall for pwrite64Func(), as opposed to pwrite64(), because pwrite64() does not work well on all distros. undo the enabling of fstatfs, as we will add this in a separate pate.
2016-08-04x86, sim: add some syscalls to X86Tony Gutierrez
this patch adds an implementation for the pwrite64 syscall and enables it for x86_64, and enables fstatfs for x86_64.
2016-08-02arm: refactor page table walkingCurtis Dunham
Introduce and use a lookup table. Using fetchDescriptor() rather than DMA cleanly handles nested paging. Change-Id: I69ec762f176bd752ba1040890e731826b58d15a6
2016-08-02arm: warn not fail on use of missing miscreg CNTHCTL_EL2Dylan Johnson
During host bootup, KVM reads/writes to CNTHCTL_EL2. Because this miscreg has not been implemented, the simulation would end there. This patch causes the simulation to warn about the read/write instead of fail. Change-Id: If034bfd0818a9a5e50c5fe86609e945258c96fa3
2016-08-02arm: Check TLB stage 2 permissions in AArch64Dylan Johnson
This fixes a bug where stage 2 lookups used the AArch32 permissions rules even if we were executing in AArch64 mode. Change-Id: Ia40758f0599667ca7ca15268bd3bf051342c24c1
2016-08-02arm: correctly assign faulting IPA's to HPFAR_EL2Dylan Johnson
This patch corrects IPA reporting if the translation faults in a stage 2 lookup. Change-Id: I0b914527f8a9f98a5e980a131cf9d03e5584b4e9
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
This patch adds support for stage 2 TLBI instructions such as TLBI IPAS2E1_Xt. Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
2016-08-02arm: Fix stage 2 memory attribute checking in AArch64Dylan Johnson
Change-Id: I14c93a5460550051a12129e792a9a9bd522a145c
2016-08-02arm: Fix trapping to Hypervisor during MSR/MRS read/writeDylan Johnson
This patch restricts trapping to hypervisor only if we are in the correct exception level for the trap to happen. Change-Id: I0a382b6a572ef835ea36d2702b8a81b633bd3df0
2016-08-02arm: Fix secure state checking in various placesDylan Johnson
Faults that could potentially be routed to the hypervisor checked whether or not they were in a secure state without checking if security was enabled or not. This caused faults not to be routed correctly. This patch causes secure state checking to first ask if security is enabled. Change-Id: I179e9b181b27f552734c9bab2b18d05ac579a119
2016-08-02arm: Fix stage 2 determination in table walkerDylan Johnson
We recompute if we are doing a stage 2 walk inside of the table walker but we have already figured it out in the tlb. Pass the information in to the walk instead of recomputing it. Change-Id: I39637ce99309b2ddbc30344d45ac9ebf6a203401
2016-08-02arm: Refactor aarch64 table walk logic to remove redundancyDylan Johnson
The functional case is already handled within the fetchDescriptor() function. We can thus use that function for both atomic and functional mode when we start the table walk. Change-Id: Iacaed28cd9024d259fd37a58150efd00ff94d86e
2016-08-02arm: Add check to fault routing for hypervisor/virtualizationDylan Johnson
This patch adds the option for faults to be routed to the hypervisor using the pre-existing routeToHyp() functions that are present in each fault type. Change-Id: I9735512c094457636b9870456a5be5432288e004
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
During address translation instructions (such as AT S1E1R_Xt) the exception level can be different than the current exception level. This patch fixes how the TLB determines what EL to use during these instructions. Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
This patch adds the AArch64 instruction hvc which raises an exception from EL1 into EL2. The host OS uses this instruction to world switch into the guest. Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be
2016-08-02arm: add stage2 translation supportDylan Johnson
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
2016-08-02arm: enable EL2 supportCurtis Dunham
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
2016-08-02arm: invalidate TLB miscreg cache on modification of HSCTLRDylan Johnson
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
2016-07-21isa: Modify get/check interrupt routinesMitch Hayenga
Make it so that getInterrupt *always* returns an interrupt if checkInterrupts() returns true. This fixes/simplifies handling of interrupts on the SMT FS CPUs (currently minor).
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
Don't consult the TLB test interface for PA's returned by functional translations by the AT instruction. We implement this by chaning the ISA code to synthesize 0-length functional reads for the TLB lookup. The TLB then bypasses the final PA check in the tester if the size is zero. Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-20arm: Mark uninitialized new TLB entries as not validNikos Nikoleris
Previously when we initialized the TLB we would allocate a number of TLB entries which would be marked as valid. As a result the TLB contained an entry which would be considered a valid entry for the 0 page. Change-Id: I23ace86426a171a4f6200ebeb29ad57c21647036 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20kern, arm: Dump dmesg on kernel panic/oopsAndreas Sandberg
Add helper functions to dump the guest kernel's dmesg buffer to a text file in m5out. This functionality is split into two parts. First, a dmesg dump function that can be used in other places: void Linux::dumpDmesg(ThreadContext *, std::ostream &) This function is used to implement two PCEvents: DmesgDumpEvent and KernelPanic event. The only difference between the two is that the latter produces a gem5 panic instead of a warning in addition to dumping the kernel log. Change-Id: I6d2af1d666ace57124089648ea906f6c787ac63c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-06-18gpu-compute: Fixed a bug in decoding Atomic STTuan Ta
There is a mismatch between DataType and SrcDataType in constructing Atomic ST instruction. The mismatch causes atomic_store and atomic_store_explicit function to store incorrect value in memory.
2016-06-09gpu-compute: parametrize Wavefront sizejkalamat
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work items); replaced it with a parameter in the GPU.py configuration script. Changed all data structures dependent on the Wavefront size to be dynamically sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at initialization time.
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
Fixing an issue with regStats not calling the parent class method for most SimObjects in Gem5. This causes issues if one adds new stats in the base class (since they are never initialized properly!). Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
We want to extend the stats of objects hierarchically and thus it is necessary to register the statistics of the base-class(es), as well. For now, these are empty, but generic stats will be added there. Patch originally provided by Akash Bagdia at ARM Ltd.
2016-06-02arm: refactor page table format determinationCurtis Dunham
In particular, when EL0 is in AArch32 but EL1 is AArch64, AArch64 memory translation must be used. This is essential for typical AArch64/32 interworking use cases.
2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
The ERET instruction doesn't set PSTATE correctly in some cases (particularly when returning to aarch32 code). Among other things, this breaks EL0 thumb code when using a 64-bit kernel. This changeset updates the ERET implementation to match the ARM ARM. Change-Id: I408e7c69a23cce437859313dfe84e68744b07c98 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-06-02arm: Correctly check FP/SIMD access permission in aarch32Andreas Sandberg
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1 and higher are all 32-bit. This breaks interprocessing since an aarch64 EL1 uses different enable/disable bits. This change updates the permission checks to according to what is prescribed by the ARM ARM. Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-05-31arm: Enable LPAE support by defaultAndreas Sandberg
LPAE has been tested with Linux 4.4 and seems to work just fine. Let's enable it by default. Change-Id: Id88c6e3c91ae9c353279d42f2aa1f8a78485bd32 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-05-31arm: Correctly check translation mode (aarch64/aarch32)Andreas Sandberg
According to the ARM ARM (see AArch32.TranslateAddress in the pseudocode library), the TLB should be operating in aarch64 mode if the EL0 is aarch32 and EL1 is aarch64. This is currently not the case in gem5, which breaks 64/32 interprocessing. Update the check to match the reference manual. Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-27arm: Use the target EL state when determining fault formatAndreas Sandberg
We currently check the current state instead of the state of the target EL when determining how we report a fault. This breaks interprocessing since EL0 in aarch32 would report its fault status using the aarch32 registers even if EL1 is in aarch64. Fix this to report the fault using the format of the target EL. Change-Id: Ic080267ac210783d1e01c722a4ddaa687dce280e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
2016-05-26arm: Fix incorrect TLB permission check in aarch32Andreas Sandberg
The TLB currently assumes that the pxn bit in an LPAE page descriptor disables execution from unprivileged mode. However, according to the architecture manual, this bit should disable execution from privileged modes. Update the TLB implementation to reflect this behavior. Change-Id: I7f1bb232d7a94a93fd601a9230223195ac952947 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26arm: Make EL checks available in SE modeAndreas Sandberg
A lot of code assumes that it is possible to test what the highest EL is and if it is 64 bit. These calls currently don't work in SE mode since they rely on an instance of an ArmSystem. Change-Id: I0d1f261926a66ce3dc4fa116845ffb2a081446f2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-05-26arm: Fix heap overflow issue in Neon64Load operationAndreas Hansson
This patch fixes an issue identified by ASAN where the Neon64Load operation assumes the packet always contains 16 bytes. Change-Id: If24a7e461d60cb80970dfbe61d923d7d56926698 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-19config, x86: Properly space pad the X86IntelMPBus Entry descriptionsBjoern A. Zeeb
According to the Intel Multi Processor Specification rev 1.4 (-006) (*), section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII (blank-filled) strings<<. This patch properly pads the entries with the missing spaces at the end. (*) http://www.intel.com/design/pentium/datashts/24201606.pdf Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19x86, dev: properly space the APIC registersBjoern A. Zeeb
Registers are 0x10 and not 0x8 apart. The latter leads to invalid calculations of index in array which in turn means that we will not find the interrupt we were looking (been notified) for in the OS. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-27arm: Remove BreakPCEvent on guest kernel panicAndreas Sandberg
The LinuxArmSystem class normally provides support for panicing gem5 if the simulated kernel panics. When this is turned off (default), gem5 uses a BreakPCEvent to provide a debugger hook into the simulator when the kernel crashes. This hook unconditionally kills gem5 with a SIGTRAP unless gem5 is compiled in fast mode. This is undesirable since the panic_on_panic param already provides similar functionality. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27kvm, arm: Make GIC interrupt lines configurableAndreas Sandberg
Add support for overriding the number of interrupt lines in the ARM KvmGic. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27kvm, arm: Refactor KVM GIC deviceAndreas Sandberg
Factor out the kernel device wrapper from the KvmGIC and put it in a separate class. This will simplify a future kernel/gem5 hybrid GIC. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-15arm,dev: remove PMU assertion hit on resetBjoern A. Zeeb
Remve the assertion that we always need to add a delta larger than zero as that does not seem to be true when we hit it in the 'PMU reset cycle counter to zero' case. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-13misc: Fix issues flagged by gcc 6Andreas Hansson
A few warnings (and thus errors) pop up after being added to -Wall: 1. -Wmisleading-indentation In the auto-generated code there were instances of if/else blocks that were not indented to gcc's liking. This is addressed by adding braces. 2. -Wshift-negative-value gcc is clever enougn to consider ~0 a negative constant, and rightfully complains. This is addressed by using mask() which explicitly casts to unsigned before shifting. That is all. Porting done.
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
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