| Age | Commit message (Expand) | Author |
|---|
| 2018-01-29 | arm: DT autogeneration - Generate memory node | Glenn Bergmans |
| 2018-01-29 | arm: DT autogeneration - Device Tree generation methods | Glenn Bergmans |
| 2018-01-23 | arch-x86: Adding clflush, clflushopt, clwb instructions | Swapnil Haria |
| 2018-01-23 | arch: Remove the "arch/tlb.hh" switching header. | Gabe Black |
| 2018-01-23 | tarch, mem: Abstract the data stored in the SE page tables. | Gabe Black |
| 2018-01-23 | x86, mem: Rewrite the multilevel page table class. | Gabe Black |
| 2018-01-20 | x86, mem: Don't try to force physical addresses on the system. | Gabe Black |
| 2018-01-20 | x86, mem: Get rid of PageTableOps::getBasePtr. | Gabe Black |
| 2018-01-20 | x86, mem: Pass the multi level page table layout in as a parameter. | Gabe Black |
| 2018-01-20 | arch, mem: Make the page table lookup function return a pointer. | Gabe Black |
| 2018-01-20 | arm, base: Generalize and move the BitUnion hash struct. | Gabe Black |
| 2018-01-20 | base: Rework bitunions so they can be more flexible. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-16 | arch-riscv: Fix floating-poing op classes | Alec Roelke |
| 2018-01-16 | arch-riscv: Fix floating-point conversion bugs | Alec Roelke |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-11 | arch-riscv: Don't crash when printing unknown CSRs | Alec Roelke |
| 2018-01-11 | arm, power: Make the python TLB simobjects inherit from BaseTLB. | Gabe Black |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | arch-riscv: Make use of ImmOp's polymorphism | Alec Roelke |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-09 | cpu, power: Get rid of the remnants of the EA computation insts. | Gabe Black |
| 2018-01-09 | arm: Make translateFunctional override the base implementation. | Gabe Black |
| 2018-01-05 | arch-riscv: Ignore sched_yield syscall in SE mode | Tuan Ta |
| 2018-01-05 | arch-riscv: Ignore set_robust_list and get_robust_list syscalls | Tuan Ta |
| 2018-01-05 | arch-riscv: Add an implementation of set_tid_address syscall in RISCV | Tuan Ta |
| 2018-01-05 | arch-riscv: Correct syscall argument reg count | Alec Roelke |
| 2018-01-04 | arch-riscv: Remove "magic" syscall number constant | Alec Roelke |
| 2017-12-23 | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. | Gabe Black |
| 2017-12-23 | riscv,x86: Stop using the arch Nop machine instruction unnecessarily. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-21 | arch-arm: Fixed WFE/WFI trapping behaviour | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Hyp routed undef fault need to change its syndrome | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Fix StaticInst encoding() method | Giacomo Travaglini |
| 2017-12-19 | arch-arm: Instruction size methods in StaticInst class | Giacomo Travaglini |
| 2017-12-19 | arch-arm: Change casting type from reinterpret to static | Giacomo Travaglini |
| 2017-12-14 | arch-riscv: Define AT_RANDOM properly | Alec Roelke |
| 2017-12-14 | arch-riscv: Increase maximum stack size | Alec Roelke |
| 2017-12-14 | misc: Updates for gcc7.2 for x86 | Jason Lowe-Power |
| 2017-12-14 | x86: Use operand size 4 when it would be 2 for cmpxchg8b. | Gabe Black |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-13 | x86: Rework how "split" loads/stores are handled. | Gabe Black |
| 2017-12-08 | arm: Change access permission in TPIDRURO and TPIDRURW | Giacomo Travaglini |
| 2017-12-08 | x86,misc: add additional info on faulting X86 instruction, fetched PC | Matt Sinclair |
| 2017-12-07 | arch-riscv: Move compressed ops out of ISA | Alec Roelke |
| 2017-12-06 | x86: Split apart x87's FSW and TOP, and add a missing break. | Gabe Black |
