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AgeCommit message (Expand)Author
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
2013-02-19scons: Add warning for missing field initializersAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-15loader: add a flattened device tree blob (dtb) objectAnthony Gutierrez
2013-02-15arm: fix a page table walker issue where a page could be translated multiple ...Mrinmoy Ghosh
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15arm: fix some fp comparisons that worked by accident.Ali Saidi
2013-02-15ARM: Fix an issue with clang generating wrong code.Ali Saidi
2013-01-22x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switchNilay Vaish
2013-01-15x86 cpuid: enable clflushNilay Vaish
2013-01-15x86: implements fsin, fcos instructionsNilay Vaish
2013-01-15x86: implements emms instructionNilay Vaish
2013-01-15x86: implement fabs, fchs instructionsNilay Vaish
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-08util: add m5_fail op.Lluís Vilanova
2013-01-08arm: add access syscall for ARM SE modeMitch Hayenga
2013-01-07cpu: Flush TLBs on switchOut()Andreas Sandberg
2013-01-07arm: Invalidate cached TLB configuration in drainResumeAndreas Sandberg
2013-01-07arm: Fix draining of the pagetable walker when squashingAndreas Sandberg
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
2013-01-07arch: Add support for invalidating TLBs when drainingAndreas Sandberg
2013-01-07arch: Fix broken M5VarArgsFault initializationAndreas Sandberg
2013-01-07base: Encapsulate the underlying fields in AddrRangeAndreas Hansson
2013-01-07arm: Make ID registers ISA parametersAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2013-01-04X86: Move address based decode caching in front of the predecoder.Gabe Black
2013-01-04SPARC: Keep a copy of the current ASI in the decoder.Gabe Black
2013-01-04ARM: Keep a copy of the fpscr len and stride fields in the decoder.Gabe Black
2012-12-30x86: implement x87 fp instruction fnstswNilay Vaish
2012-12-30x86: implement x87 fp instruction fsincosNilay Vaish
2012-12-12arm: set uopSet_uop as conditional or unconditional controlNathanael Premillieu
2012-12-12arm: set movret_uop as conditional or unconditional controlNathanael Premillieu
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02mips: Remove unused Python fileAndreas Sandberg
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-11-02ISA: generic Linux thread info supportDam Sunwoo
2012-10-25arm: Use table walker clock that is inherited from CPUAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Checkpoint: Make system serialize call childrenAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-09-25ARM: added support for flattened device tree blobsDam Sunwoo
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-25arm: Use a static_assert to test that miscRegName[] is completeAndreas Sandberg
2012-09-25ARM: Inst writing to cntrlReg registers not set as control instNathanael Premillieu
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