summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Expand)Author
2018-04-19arch-arm: Fix Unknown Instruction disassembleGiacomo Travaglini
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
2018-04-18arch-arm: Fix FPEXC32_EL2 to FPEXC mappingChuan Zhu
2018-04-18arch-arm: Adding MiscReg Priv (EL1) global flagGiacomo Travaglini
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
2018-04-17arch-arm: Fix secure MiscReg access when EL3 is not AArch32Giacomo Travaglini
2018-04-10arch-arm: Fix mrc,mcr to cop14 disassembleGiacomo Travaglini
2018-04-06arch: alpha: Fix an 8 year old bug from the transition to pc objects.Gabe Black
2018-04-06arch-arm: Add support for Tarmac trace generationGiacomo Travaglini
2018-04-06arch-arm: Add support for Tarmac trace-based simulationGiacomo Travaglini
2018-04-06arch-arm: Fix AArch32 branch instructions disassembleGiacomo Travaglini
2018-04-06arch-arm: Fix secure write of SCTLR when EL3 is AArch64Giacomo Travaglini
2018-04-06arch-arm: Correct mcrr,mrrc disassembleGiacomo Travaglini
2018-03-27arch: cpu: Make the ExtMachInst type a template argument in InstMap.Gabe Black
2018-03-27sparc: Add some missing M5_FALLTHROUGHs and breaks.Gabe Black
2018-03-26arch: Fix all override related warnings.Gabe Black
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black
2018-03-23arch-arm: Distinguish IS TLBI from non-ISGiacomo Travaglini
2018-03-23arch-arm: Created function for TLB ASID InvalidationGiacomo Travaglini
2018-03-20arch, arm: Fix implicit-fallthrough GCC warningsChun-Chen Hsu
2018-03-20riscv: throw IllegalInstFault when decoding invalid instructionsTuan Ta
2018-03-15arm: Fix implicit-fallthrough warnings when building with gcc-7+Siddhesh Poyarekar
2018-03-15arch-x86,sim-se: Enable prlimit syscallJason Lowe-Power
2018-03-15arch-x86,sim-se: Bump kernel version to 3.2Jason Lowe-Power
2018-03-15arch-arm: Fix unused variable warning in faults.ccNikos Nikoleris
2018-03-15x86: Add bitfields which can gather/scatter bases and limits.Gabe Black
2018-03-14x86: Simplify the implementations of RDTSC and RDTSCP slightly.Gabe Black
2018-03-14x86: Implement the RDTSCP instruction.Gabe Black
2018-03-14x86: Mark the RDTSC instruction as .serialize_before.Gabe Black
2018-03-14x86: Replace the .serializing directive with .serialize_(before|after).Gabe Black
2018-03-14arm: Fix maybe-uninitialized GCC warningsChun-Chen Hsu
2018-03-14arch-arm: ERET from AArch64 to AArch32 ignore MSBsGiacomo Travaglini
2018-03-12arch-arm: Adding IPA-Based Invalidating instructionsGiacomo Travaglini
2018-03-12arch-arm: Implement missing aarch32 TLBI registersGiacomo Travaglini
2018-03-08sparc: Passify a new g++ warning.Gabe Black
2018-03-08arch-arm: Enable Debug IFSC when faulting to aarch64 modeGiacomo Travaglini
2018-03-08arch-arm: Fix FSC generation in AbortFaultGiacomo Travaglini
2018-03-08arch-arm: Introduce update method in ArmFault classGiacomo Travaglini
2018-03-08arch-arm: Fix PCAlignmentFault routing to HypervisorGiacomo Travaglini
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
2018-03-06arm: Remove ignored const qualifierSiddhesh Poyarekar
2018-02-24sparc: Fix FS Checkpoint loadingKhalique
2018-02-20arch-arm: Make hlt64 a mem barrier with semihostingGiacomo Travaglini
2018-02-20arch-arm: Add AArch32 HLT Semihosting interfaceGiacomo Travaglini
2018-02-20arch-arm: Add AArch32 SVC Semihosting interfaceGiacomo Travaglini
2018-02-20arch-arm: Adding isa templates for semihosting opsGiacomo Travaglini
2018-02-20arch-arm: HLT using immediate when checking for semihostingGiacomo Travaglini
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 02:58:57 +0000