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path: root/src/arch
AgeCommit message (Expand)Author
2017-01-03sim: Remove redundant export_method_cxx_predeclsAndreas Sandberg
2016-12-19arm: provide correct timer availability in ID_PFR1 registerCurtis Dunham
2016-12-19arm: compute ID_AA64PFR{0,1}_EL1 registersCurtis Dunham
2016-12-19arm: compute ID_PFR{0,1} registersCurtis Dunham
2016-12-19arm: miscreg refactoringCurtis Dunham
2016-12-19arm: audit SCTLRCurtis Dunham
2016-12-19arm: remove SCTLR.FICurtis Dunham
2016-12-19arm: update AArch{64,32} register mappingsCurtis Dunham
2016-12-15syscall_emul: implement fallocateBrandon Potter
2016-12-15syscall_emul: add support for x86 statfs system callsBrandon Potter
2016-12-02hsail: disable asserts to allow immediate operands i.e. 0 with loadsBrandon Potter
2016-12-02hsail: add stub type and stub out several instructionsBrandon Potter
2016-12-02hsail: add popcount type and generate popcount instructionsBrandon Potter
2016-12-02hsail: add a wavesize case statement to register operand codeBrandon Potter
2016-12-02hsail: generate mov instructions for more arith_types and bit_typesBrandon Potter
2016-12-02hsail: fix unsigned offset bug in address calculationTony Gutierrez
2016-11-30riscv: [Patch 7/5] Corrected LRSC semanticsAlec Roelke
2016-11-30riscv: [Patch 6/5] Improve Linux emulation for RISC-VAlec Roelke
2016-11-30riscv: [Patch 5/5] Added missing support for timing CPU modelsAlec Roelke
2016-11-30riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64AAlec Roelke
2016-11-30riscv: [Patch 3/5] Added RISCV floating point extensions RV64FDAlec Roelke
2016-11-30riscv: [Patch 2/5] Added RISC-V multiply extension RV64MAlec Roelke
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke
2016-11-21x86: fix issue with casting in Cvtf2iTony Gutierrez
2016-11-19x86: fix loading/storing of Float80 typesTony Gutierrez
2016-11-17alpha: Remove ALPHA tru64 support and associated testsAndreas Hansson
2016-10-26hsail,gpu-compute: fixes to appease clang++Tony Gutierrez
2016-10-26dev: Add m5 op to toggle synchronization for dist-gem5.Michael LeBeane
2016-10-26gpu-compute: support in-order data delivery in GM pipeTony Gutierrez
2016-10-26gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()Tony Gutierrez
2016-10-26gpu-compute, hsail: make the PC a byte address, not an instruction indexTony Gutierrez
2016-10-26gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WFTony Gutierrez
2016-10-26gpu-compute, hsail: call discardFetch() from the WFTony Gutierrez
2016-10-26hsail, gpu-compute: remove doGm/SmReturn add completeAccTony Gutierrez
2016-10-26gpu-compute: remove inst enums and use bit flag for attributesTony Gutierrez
2016-10-26gpu-compute: move disassemle() implementation to GPUStaticInstTony Gutierrez
2016-10-26gpu-compute, arch: add some methods to the base inst classes for ISA supportTony Gutierrez
2016-10-15cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClassFernando Endo
2016-10-13isa,arm: Add missing AArch32 FP instructionsMitch Hayenga
2016-10-04kvm: Adding details to kvm page fault in x86Alexandru Dutu
2016-09-16hsail: Fix disassembly of load instruction with 3 destination operandsAlexandru Dutu
2016-09-16gpu-compute: Refactoring Wavefront::dynWaveIdAlexandru Dutu
2016-09-16gpu-compute: Wavefront refactoringAlexandru Dutu
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
2016-09-13x86: Force strict ordering for memory mapped m5opsMichael LeBeane
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-08-05sim: fix issues with pwrite(); don't enable fstatfsTony Gutierrez
2016-08-04x86, sim: add some syscalls to X86Tony Gutierrez
2016-08-02arm: refactor page table walkingCurtis Dunham
2016-08-02arm: warn not fail on use of missing miscreg CNTHCTL_EL2Dylan Johnson