Age | Commit message (Collapse) | Author |
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fix addr alignment problem
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extra : convert_revision : c691611d4d32bc95d0ae30243b30cd6634e7772b
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into zower.eecs.umich.edu:/eecshome/m5/newmemmid
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
hand merge
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extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : c358d5e3211756bbf905eef2a62b65a2e56a86f3
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src/arch/SConscript:
add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits
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extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
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src/arch/sparc/process.cc:
MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
Sparc version of this file.
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extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
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into ewok.(none):/home/gblack/m5/newmemo3
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extra : convert_revision : e8d6ce19a83fe526112c1dd61c48196eb8c0951f
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : f540987901994fe9dc023587fd555efb2dbf24bf
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src/arch/sparc/SConscript:
Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
update asi names for how they're listed in the supplement
add asis
add more asi functions
src/arch/sparc/isa_traits.hh:
move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add mmu registers to tlb
get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
first cut at sparc tlb
src/arch/sparc/vtophys.hh:
pagatable nedes to be included here
src/mem/request.hh:
add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
fix incorrect definition of LL
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extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3
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src/arch/sparc/isa/base.isa:
Fix a constant.
src/arch/sparc/isa/decoder.isa:
Made carry calculation more consistent.
src/arch/sparc/isa/operands.isa:
Use the right constant.
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extra : convert_revision : 25b3a09ff20d4b8e1a95ee8a983d14ef3cfe73bb
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extra : convert_revision : 378b2d9791e6282539900a2261ad2275d726b4be
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
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extra : convert_revision : 8707bbed2aeb80613f86503e92b63853767adaa9
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manual of what happens during a trap says it should be 0, and other places say it doesn't matter.
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extra : convert_revision : 9ecb6af06657e936a208cbeb8e4a18305869b949
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description.
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
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configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
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extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
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make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
src/arch/sparc/interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
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extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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extra : convert_revision : cda58e6e63f2f909b85a510fb76d35d49d8042b9
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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extra : convert_revision : 753831a9f6f79d07e6ee122ab894e24161d2e722
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into vm1.(none):/home/stever/bk/newmem-head
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extra : convert_revision : faab7569deefde94c20133b2f70a8567bcaa2960
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extra : convert_revision : 88fdaa403fe6d083f8c8fc064cb0d0d6a8b8daf8
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
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src/arch/alpha/interrupts.hh:
No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
Fix broken if statement from PcPAL updates, and properly populate the request fields.
Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
Populate request fields properly.
src/cpu/simple/base.cc:
Update for interrupt stuff.
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extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
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extra : convert_revision : 863d395f8e7c8ee2aec708ffcef842317ec9a89b
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src/arch/alpha/faults.hh:
Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
Only use tlb.hh in FS
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extra : convert_revision : 91ea61f2e7970e7146b6d407ee250fcb20cd4d48
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use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?
src/arch/sparc/faults.cc:
set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
fix endian issues with condition codes
src/arch/sparc/tlb.hh:
add implemented physical addres constants
src/arch/sparc/utility.hh:
add tlb.hh to utilities
src/base/loader/raw_object.cc:
add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
use memcpy instead of bcopy
src/cpu/exetrace.cc:
clean up printing a bit more
src/cpu/m5legion_interface.h:
add tons to the shared interface
src/dev/ethertap.cc:
s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
hack to make sure htole() works...
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extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
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the virtual address.
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Ctrl_Base_DepTag.
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properly.
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extra : convert_revision : f2cad8a5879999438ba9b05f15a91320e7a4cc4a
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code to read and write the strand_sts_reg, and made restored a Priv instruction.
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constants.hh and isa_traits.cc
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called from the class's constructor.
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