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2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
The ISA parser used to generate different copies of exec functions for each exec context class a particular CPU wanted to use. That's since been changed so that those functions take a pointer to the base ExecContext, so the code which would generate those extra functions can be removed, and some functions which used to be templated on an ExecContext subclass can be untemplated, or minimally less templated. Now that some functions aren't going to be instantiated multiple times with different signatures, there are also opportunities to collapse templates and make many instruction definitions simpler within the parser. Since those changes will be less mechanical, they're left for later changes and will probably be done in smaller increments. Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea Reviewed-on: https://gem5-review.googlesource.com/5381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31x86: Fix VEX instruction decoding.Gabe Black
When decoding VEX prefixed instructions, the x86 predecoder wasn't walking past the opcode byte and so was also interpreting it as the modRM byte. Reported-by: likunxi@fas.harvard.edu Change-Id: I6d4bdabfa03411704c48d905c50c7b23072fc615 Reviewed-on: https://gem5-review.googlesource.com/5281 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-20arch-arm: RBIT instruction using mirroring funcGiacomo Travaglini
The high speed bit-reversing function is now used for the Aarch64/32 RBIT instruction implementation. Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5262 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-17scons: Stop generating inc.d in the isa parser.Gabe Black
Generating dependency/build product information in the isa parser breaks scons idea of how a build is supposed to work. Arm twisting it into working forced a lot of false dependencies which slowed down the build. Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca Reviewed-on: https://gem5-review.googlesource.com/5081 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-17arch-arm: Fix inverted 32/64-bit check in GDBBoris Shingarov
Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0 Reviewed-on: https://gem5-review.googlesource.com/4720 Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-13arch-arm: Signal an event when executing store exclusivesNikos Nikoleris
When a store exclusive is executed, whether it is successful or not, the exclusives monitor is cleared and therefore we need to signal an event for the PE. Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4480 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-13mem: Signal the local monitor when clearing the global monitorNikos Nikoleris
ARM systems require the coordination of the global and local monitors. When the system is run without caches the global monitor is implemented in the abstract memory object. This change adds a callback from the abstract memory that notifies the local monitor when the global monitor is cleared. Additionally, for ARM systems the local monitor signals the event register and wakes the thread context up. Subsequent wait-for-event (WFE) instructions will be immediately signaled. Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3760 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-09-27arch-x86: fix CondInst decoding for MOV to Control RegistersBjoern A. Zeeb
MOV Rd,Cd is MR encoded but the control register is operand 2 not operand 1 hence this needs to be MODRM_REG not MODRM_RM. While MOV Cd,Rd is RM encoded registers are also swapped, so it also needs to be MODRM_REG as well (as it already correctly is). This fixes incorrect UD2 reportings leading to invalid traps reported in O3 on X86 FS introduced with 4e939a7 . Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8 Reviewed-on: https://gem5-review.googlesource.com/4861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-27arch: change panic for Vector traceData to warn_onceBjoern A. Zeeb
Make the traceData panic for Vectors a warn_once. It's a pity it's not implemented but it's not a reason to abort the simulation entirely. Change-Id: I5e97258fd4e3fa385cfe0c4b400524d1f7b154df Reviewed-on: https://gem5-review.googlesource.com/4860 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-21alpha: Move some initialization logic from loadState into unserialize.Gabe Black
The primary difference between loadState and unserialize, at least when eventually using the default SimObject implementation of loadState, is that unserialize is called only if there's a corresponding section in the checkpoint being restored. In this particular case, the AlphaProcess class calls the generic Process unserialize function, and that does other critical initialization like set up the processes page table. If the unserialize function isn't called, other serious problems would break the simulation anyway. This removes the final custom implementation of loadState. Change-Id: If50062392196bd37efd5ba04fd7aee6907b00dc6 Reviewed-on: https://gem5-review.googlesource.com/4741 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-20kvm: arm: Get rid of functions which just wrap the subclasses version.Gabe Black
The MuxingKvmGic class defined a few functions related to checkpointing which did nothing other than call the underlying Pl390 implementation. These are unnecessary in general, and are particularly unnecessary for the loadState function which is a very lightly used part of the checkpointing interface. It's not actually defined in Pl390 either, and falls through to the underlying implementation. Change-Id: I84aae13d4966df0f4fdd1a72aee0bf1af01392ff Reviewed-on: https://gem5-review.googlesource.com/4760 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-11stats: Move the swpipl function into the Alpha kernel stats.Gabe Black
This stat is only incremented by Alpha. Also move the _hwrei into the Alpha stats object since it's the class that actually sets up and maintains that value and it probably should have been there all along. Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0 Reviewed-on: https://gem5-review.googlesource.com/4601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-11stats: Get rid of some kernel stats related cruft.Gabe Black
The kernel stat mechanism should really be refactored and moved somewhere else, but in the mean time there's some old cruft that can be cleared away. Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86 Reviewed-on: https://gem5-review.googlesource.com/4600 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30arch-arm: Only increment SW PMU counters on writes to PMSWINCJose Marinho
When writing a bitmask of counters to PMSWINC, the PMU currently increments the corresponding counters regardless of what they are configured to count. According to the ARM ARM (D5.10.4), counters should only be updated if they have been configured to count software events (event type 0). Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4285 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30arch-arm: Add missing override keywords in fault.hhAndreas Sandberg
Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4284 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-08-30arch-x86: Add missing override in the X86 TLBAndreas Sandberg
Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4283 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-08-30arch-sparc: Add a FaultVals instantiation for VecDisabledAndreas Sandberg
Recent gcc versions complain about a missing VecDisabled not having an explicit FaultVals instantiation. Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4282 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-30arch-alpha: Add missing overridesAndreas Sandberg
Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4281 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-28x86: Use the new CondInst format for moves to/from control registers.Gabe Black
The condition is whether the control register index is valid. Change-Id: I8a225fcfd4955032b5bbf7d3392ee5bcc7d6bc64 Reviewed-on: https://gem5-review.googlesource.com/4581 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-28x86: Add a "CondInst" format for conditionally decoded instructions.Gabe Black
A condition can be specified which will tell the decoder whether to return the instruction being requested, or, if the condition fails, UD2. Change-Id: I0f1c075deb10754ce1dd88be1726a196294e41fd Reviewed-on: https://gem5-review.googlesource.com/4580 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-01arch-arm: Use named constants for m5op instructionsAndreas Sandberg
Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4263 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01kvm, arm: Switch to the device EQ when accessing ISA devicesAndreas Sandberg
ISA devices typically run in the device event queue. Previously, we assumed that devices would perform their own EQ migrations as needed. This isn't ideal since it means we have different conventions for IO devices and ISA devices. Switch to doing migrations in the KVM CPU instead to make the behavior consistent. Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4288 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
Old ARM systems used to pass the machine type in the ATAGS list passed to the kernel. This has been largely deprecated by the introduction of device trees. Switch to the DTOnly machine type by default in gem5 since all new platforms and kernel will require this behavior. Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4260 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
This fixes the function call to clone in syscall_emul.hh where the x86 version should be called before the base implementation of clone. Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3902 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17x86: Add stats to X86 TLBSwapnil Haria
Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3980 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17riscv: Define register index constants using literalsAlec Roelke
To make it clearer what the register indices are for the semantically meaningful registers defined by src/arch/riscv/registers.hh, the constants that were defined using other constants were changed to use the literal values of those constants. This also removes the need to use the M5_VAR_USED attribute. Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61 Reviewed-on: https://gem5-review.googlesource.com/4080 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
When both the C and C++ versions are visible, the compiler will complain that it doesn't know which one to use. By specifying the std namespace, it will know to use the C++ version. Change-Id: Ie1bbe1d95eadbad9644b4915c21f924d7d5c0b22 Reviewed-on: https://gem5-review.googlesource.com/4060 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
Three of the constants defined in arch/riscv/registers.hh (ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause the compiler to warn that they are unused, which results in an error. This patch adds M5_VAR_USED attributes to them to stop this. Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457 Reviewed-on: https://gem5-review.googlesource.com/4040 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-13arch-arm: fix ldm of pc interswitching branchGedare Bloom
The LDM instruction that loads to the PC causes a branch to the instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes. The interswitch is broken prior to this commit, with LDM to the PC ignoring the switch. Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05 Reviewed-on: https://gem5-review.googlesource.com/3520 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12mips, x86: Refactor some Event subclasses into lambdasSean Wilson
Change-Id: I09570e569efe55f5502bc201e03456738999e714 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3920 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
This patch adds compatibility with the 64-bit compressed extension to the RISC-V ISA, RV64C. Current versions of the toolchain may use compressed instructions in glibc by default, which can only be overridden by recompiling the entire toolchain (simply adding "-march=rv64g" or "-march=rv64imafd" when compiling a binary is not sufficient to use uncompressed instructions in glibc functions in the binary). [Update diassembly generation for new RegId type.] [Rebase onto master.] Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4 Reviewed-on: https://gem5-review.googlesource.com/3860 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
This patch restructures the RISC-V ISA description to use fewer classes and improve its ability to be extended with nonstandard extensions in the future. It also cleans up the disassembly for some of the CSR and system instructions by removing source and destination registers for instructions that don't have any. [Fix class UImmOp to have an "imm" member rather than "uimm".] [Update disassembly generation for new RegId class.] Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9 Reviewed-on: https://gem5-review.googlesource.com/3800 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-10arch-arm: Support PMU evens in the 0x4000-0x4040 rangeJose Marinho
ARMv8.1 added a second architected event range, 0x4000-0x4040. Events in this range are discovered using the high word of PMCEID{0,1}_EL0 Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3960
2017-07-07kvm, arm: don't create interrupt events while saving GIC stateCurtis Dunham
If an interrupt was pending according to Kvm state during a drain, the Pl390 model would create an interrupt event that could not be serviced, preventing the system from draining. The proper behavior is for the Pl390 not actively being used for simulation to just skip the GIC state machine that delivers interrupts. Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3661 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-07kvm, arm: Don't forward IRQ/FIQ when using the kernel's GICAndreas Sandberg
The BaseArmKvmCPU is responsible for forwarding the IRQ and FIQ signals from gem5's simulated GIC to KVM. However, these signals shouldn't be used when the in-kernel GIC emulator is used. Instead of delivering the interrupts to the guest, we should just ignore them since any such pending interrupts are likely to be an artifact of CPU switching or incorrect draining. Change-Id: I083b72639384272157f92f44a6606bdf0be7413c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3660
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
2017-07-05arch: added generic vector registerRekai Gonzalez-Alberquilla
This commit adds a new generic vector register to have a cleaner implementation of SIMD ISAs. Nathanael's idea, Rekai's implementation. Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2704 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
With the hierarchical RegId there are a lot of functions that are redundant now. The idea behind the simplification is that instead of having the regId, telling which kind of register read/write/rename/lookup/etc. and then the function panic_if'ing if the regId is not of the appropriate type, we provide an interface that decides what kind of register to read depending on the register type of the given regId. Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2702
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
2017-07-05arm,kvm: update CP15 timer model when exiting KvmCurtis Dunham
The ARM MiscRegs implementation has two interfaces: 'normal' and 'no effect'. The latter acts as a way to access the backing store without architectural 'effects'. For instance, a normal write to a timer compare value would call into the timer model to emulate the device. The 'no effect' interface, however, would just write the value into the register backing store and do nothing else. For Kvm execution, a delicate balance must be struck for the timer device specifically. We need the code in the model to be run, because it contains state other than the register backing store that must stay in sync. On the other hand, we don't necessarily want the timer model to schedule gem5 events when this happens. In this commit, we ensure that we use the 'effectful' MiscReg interface when copying the CP15 timer registers from Kvm back into gem5. The prior commit makes sure that this doesn't generate unnecessary timer events or interrupts. Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9 Reviewed-on: https://gem5-review.googlesource.com/3543 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05kvm: move Kvm check from ARM Kvm GIC to SystemCurtis Dunham
The check was nearly completely generic anyway, with the exception of the Kvm CPU type. This will make it easier for other parts of the codebase to do similar checks. Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da Reviewed-on: https://gem5-review.googlesource.com/3540 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-22arm,sim: fix context switch stats dumps for ARM64/LinuxPaul Rosenfeld
32bit and 64bit Linux have different arguments passed to the __switch_to() function that gem5 hooks into in order to collect context switch statistics. 64bit Linux provides the task_struct pointer to the next task that will be switched to, which means we don't have to look up the task_struct from thread_info as we do in 32bit ARM Linux. This patch adds a second set of accessors to ThreadInfo to extract details such as the pid, tgid, task name, etc., directly from a task_struct. The existing accessors maintain their existing behavior by first looking up the task_struct and then calling these new accessors. A 64-bit variant of the DumpStatsPCEvent class is added that uses these new accessors to get the task details for the context switch dumps directly from the task_struct passed to __switch_to(). Change-Id: I63c4b3e1ad64446751a91f6340901d5180d7382d Reviewed-on: https://gem5-review.googlesource.com/2640 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-20sim, x86: Replace EventWrapper use with EventFunctionWrapperSean Wilson
Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3749 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-06-20arm: Replace EventWrapper use with EventFunctionWrapperSean Wilson
Change-Id: I08de5f72513645d1fe92bde99fa205dde897e951 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3747 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-15x86: Add consistent overrides to process.hhSean Wilson
Change-Id: I912601b6f781a0bbedd06583c059589374f6d5c6 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3720 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Joe Gross <joe.gross@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-15x86: Fixed remote debugging of simulated codeMatthias Hille
GDB breaks if more bytes are sent than the transmitted registers actually need. Therefore the GdbRegCache struct needs to be packed to prevent padding at the end. Change-Id: Ib2c14eb70becdac609eb4f475d5dddbd5bcc60da Signed-off-by: Matthias Hille <matthiashille8@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/3020 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-26x86: Rework how VEX prefixes are decoded.Gabe Black
Remove redundant information from the ExtMachInst, hash the vex information to ensure the decode cache works properly, print the vex info when printing an ExtMachInst, consider the vex info when comparing two ExtMachInsts, fold the info from the vex prefixes into existing settings, remove redundant decode code, handle vex prefixes one byte at a time and don't bother building up the entire prefix, and let instructions that care about vex use it in their implementation, instead of developing an entire parallel decode tree. This also eliminates the error prone vex immediate decode table which was incomplete and would result in an out of bounds access for incorrectly encoded instructions or when the CPU was mispeculating, as it was (as far as I can tell) redundant with the tables that already existed for two and three byte opcodes. There were differences, but I think those may have been mistakes based on the documentation I found. Also, in 32 bit mode, the VEX prefixes might actually be LDS or LES instructions which are still legal in that mode. A valid VEX prefix would look like an LDS/LES with an otherwise invalid modrm encoding, so use that as a signal to abort processing the VEX and turn the instruction into an LES/LDS as appropriate. Change-Id: Icb367eaaa35590692df1c98862f315da4c139f5c Reviewed-on: https://gem5-review.googlesource.com/3501 Reviewed-by: Joe Gross <joe.gross@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-05-25x86: sim: Make 32 bit x86 processes work again.Gabe Black
When the LiveProcess class was renamed to be just Process, the CL author also changed the syscall function from a virtual function into a regular one. Unfortunately, the I386Process class overrode the syscall function to adjust the return address so that control would return to the right place. Without that adjustment, 32 bit x86 process would segfault and die immediately after their first system call. This change reinstates the virtual specifier on the base syscall function, and adds an override keyword on the I386Process's version so that it won't be orphaned again in the future. It also fixes some small style issues the style checker script complained about. Change-Id: I0d1178ea0eda6676050c8fc043820a2bb4d99c0d Reviewed-on: https://gem5-review.googlesource.com/3500 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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