| Age | Commit message (Expand) | Author |
|---|
| 2018-02-07 | arch-arm: Turn dc ivac to dc civac when some conditions are met | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Fix printing of the data cache maintenance instructions | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Fix cache line size for cache maintenace inst | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Fault when dc ivac is executed from EL0 | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Change function name for banked miscregs | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Fix AArch32 SETEND Instruction | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Correct Illegal Exception Return detection | Giacomo Travaglini |
| 2018-02-07 | arch-arm: ELUsingAArch32K from armarm pseudocode | Giacomo Travaglini |
| 2018-02-07 | arch-arm: isSecureBelow from armarm pseudocode | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Fix incorrect assumptions in ELIs64 | Chuan Zhu |
| 2018-02-05 | arch-arm: Removing Serializing flag from ISB | Giacomo Travaglini |
| 2018-02-01 | alpha: fix for no 'break' in the case statement | Sujay Phadke |
| 2018-01-31 | arch-x86: consistent style of comments in system files | Christian Menard |
| 2018-01-30 | arch-x86: Granularity bit and segment limit | Maximilian Stein |
| 2018-01-29 | riscv: Add overrides to various StaticInst methods. | Gabe Black |
| 2018-01-29 | arch-arm: understandably initialize register permissions | Curtis Dunham |
| 2018-01-29 | arm: extend MiscReg metadata structures | Curtis Dunham |
| 2018-01-29 | arch-arm: understandably initialize register mappings | Curtis Dunham |
| 2018-01-29 | arm: DT autogeneration - Generate memory node | Glenn Bergmans |
| 2018-01-29 | arm: DT autogeneration - Device Tree generation methods | Glenn Bergmans |
| 2018-01-23 | arch-x86: Adding clflush, clflushopt, clwb instructions | Swapnil Haria |
| 2018-01-23 | arch: Remove the "arch/tlb.hh" switching header. | Gabe Black |
| 2018-01-23 | tarch, mem: Abstract the data stored in the SE page tables. | Gabe Black |
| 2018-01-23 | x86, mem: Rewrite the multilevel page table class. | Gabe Black |
| 2018-01-20 | x86, mem: Don't try to force physical addresses on the system. | Gabe Black |
| 2018-01-20 | x86, mem: Get rid of PageTableOps::getBasePtr. | Gabe Black |
| 2018-01-20 | x86, mem: Pass the multi level page table layout in as a parameter. | Gabe Black |
| 2018-01-20 | arch, mem: Make the page table lookup function return a pointer. | Gabe Black |
| 2018-01-20 | arm, base: Generalize and move the BitUnion hash struct. | Gabe Black |
| 2018-01-20 | base: Rework bitunions so they can be more flexible. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-16 | arch-riscv: Fix floating-poing op classes | Alec Roelke |
| 2018-01-16 | arch-riscv: Fix floating-point conversion bugs | Alec Roelke |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-11 | arch-riscv: Don't crash when printing unknown CSRs | Alec Roelke |
| 2018-01-11 | arm, power: Make the python TLB simobjects inherit from BaseTLB. | Gabe Black |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | arch-riscv: Make use of ImmOp's polymorphism | Alec Roelke |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-09 | cpu, power: Get rid of the remnants of the EA computation insts. | Gabe Black |
| 2018-01-09 | arm: Make translateFunctional override the base implementation. | Gabe Black |
| 2018-01-05 | arch-riscv: Ignore sched_yield syscall in SE mode | Tuan Ta |
| 2018-01-05 | arch-riscv: Ignore set_robust_list and get_robust_list syscalls | Tuan Ta |
| 2018-01-05 | arch-riscv: Add an implementation of set_tid_address syscall in RISCV | Tuan Ta |
| 2018-01-05 | arch-riscv: Correct syscall argument reg count | Alec Roelke |
| 2018-01-04 | arch-riscv: Remove "magic" syscall number constant | Alec Roelke |
| 2017-12-23 | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. | Gabe Black |
