Age | Commit message (Collapse) | Author |
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Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself.
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actually work.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
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extra : convert_revision : f3d193dd1e0b82c496d8224f014123b7cb028c02
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
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extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
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out-of-order interactions in the 21264.
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useful for x86.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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different sets of inputs.
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what bits decode is done on to reflect where clumps of instructions are.
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extra : convert_revision : 8768676eac25e6a4f0dc50ce2dc576bdcdd6e025
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rename : src/arch/x86/isa/decoder.isa => src/arch/x86/isa/decoder/decoder.isa
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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src/arch/alpha/predecoder.hh:
src/arch/sparc/predecoder.hh:
Put in a missing include
src/cpu/exetrace.cc:
Convert the legion lockstep stuff from makeExtMI to the predecoder object.
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down farther.
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This isn't necessary since they don't use the extended fields, but it's more consistent and more correct.
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src/arch/x86/predecoder.cc:
File for the x86 predecoder process function.
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byte opcodes.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge
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extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
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adding predecoding functionality to x86.
src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899
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Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
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extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
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src/arch/sparc/ua2005.cc:
fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to
check if were suspended and interrupt at the guess time
src/base/traceflags.py:
add trace flag for Iob
src/cpu/simple/base.cc:
Use Quisce instead of IPI trace flag
src/dev/sparc/iob.cc:
add some Dprintfs
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into zeep.pool:/z/saidi/work/m5.newmem
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src/arch/sparc/miscregfile.cc:
this code should be in readFSreg
src/arch/sparc/ua2005.cc:
move code froh miscregfile to ua2005.cc
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floating point condition codes with prediction.
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace-test
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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extra : convert_revision : 82a956ffc1bedb2c0d05c4ea3469f843f559a475
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bit syscall table into it's own file. Corrected problems with the stat structure. These should be tested on 64 bit x86 and SPARC machines.
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src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
some constants for the strand status register
src/arch/sparc/ua2005.cc:
properly implement the strand status register
src/dev/sparc/iob.cc:
implement ipi generation properly
src/sim/system.cc:
call into the ISA to start the CPU (or not)
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extra : convert_revision : 0003b2032337d8a031a9fc044da726dbb2a9e36f
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src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add CMT ASI registers
src/arch/sparc/tlb.cc:
Panic if any of the CMT registers are being accessed
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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