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2006-10-31Get rid of old, commented out code.Gabe Black
--HG-- extra : convert_revision : 46e9f26917efab642b80ea9e4303ec95d43d935e
2006-10-31Move IntrFlag into the MiscRegFile and get rid of specialized accessor ↵Gabe Black
functions. --HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
2006-10-31Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes ↵Gabe Black
more neutral names. --HG-- extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
2006-10-29Move the mem classes into util.isa so that multiple inheritance can be used ↵Gabe Black
in the future for micro insts. --HG-- extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
2006-10-29Fix when the IsDelayedCommit flag is set.Gabe Black
--HG-- extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
2006-10-29Bring casa and casxa up to dateGabe Black
src/arch/sparc/isa/decoder.isa: Fix up the casa and casxa instructions. src/arch/sparc/isa/formats/formats.isa: This is handled in loadstore.isa now src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version. src/arch/sparc/isa/formats/mem/mem.isa: The cas format is handled in loadstore.isa as well now. src/arch/sparc/isa/formats/mem/util.isa: Reorganized things a bit to better support cas --HG-- extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
2006-10-29Fixed ldstub to use the right format, and made the load/store operations use ↵Gabe Black
the integer microcode register. --HG-- extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
2006-10-29Add an integer microcode register.Gabe Black
--HG-- extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
2006-10-27Got rid of some outdated comments.Gabe Black
--HG-- extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
2006-10-27Made the regfile compatible with the new definitions in MiscRegFileGabe Black
--HG-- extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
2006-10-27Clean up MiscRegFileGabe Black
--HG-- extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
2006-10-26Reorganized the MiscRegFileGabe Black
--HG-- extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
2006-10-26Cleaned up the decoder slightly.Gabe Black
--HG-- extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
2006-10-26Changed the number of register windows to be more realistic.Gabe Black
--HG-- extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
2006-10-26Got rid of some debug outputGabe Black
--HG-- extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
2006-10-26Change the default function from setMiscRegWithEffect to setMiscRegGabe Black
--HG-- extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
2006-10-25Fixed the priv instruction format.Gabe Black
src/arch/sparc/isa/formats/priv.isa: Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated. src/arch/sparc/isa/operands.isa: Added an Hpstate operand, and adjusted the numbering. --HG-- extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
2006-10-25Implemented the saved and restored instructions, fixed up register window ↵Gabe Black
instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction. --HG-- extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
2006-10-25Fixed the bitfield FCN to include the right bits.Gabe Black
--HG-- extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
2006-10-25Implemented the SPARC fill and spill handlers.Gabe Black
src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE src/arch/sparc/process.cc: src/arch/sparc/process.hh: Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart. --HG-- extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
2006-10-24Replace the Alpha No op with a SPARC one.Gabe Black
--HG-- extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
2006-10-23Move around more SPARC memory code, and make block memory operations work ↵Gabe Black
with the timing cpu --HG-- extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
2006-10-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
2006-10-23Broke Load/Store instructions into microcode, and partially refactored ↵Gabe Black
memory operations in the SPARC ISA description. --HG-- rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa extra : convert_revision : dbbb00f997a102871b084b209b9fa08c5e1853ee
2006-10-23Start making memory ops work with InitiateAcc and CompleteAcc, and some ↵Gabe Black
minor cleanups --HG-- extra : convert_revision : 178a8c5d0506c75ad7a7e8d691c8863235ed7e95
2006-10-23Change the default constructors to take ExtMachInsts rather than regular ↵Gabe Black
MachInsts --HG-- extra : convert_revision : 8fa34f82e0cbf5ce81775d572b182826c578581f
2006-10-21Tweak a few things for better page fault debugging.Steve Reinhardt
src/sim/faults.cc: Fix fault message. src/kern/tru64/tru64.hh: Add DPRINTF to see where new thread stacks are allocated. src/arch/alpha/faults.cc: Add print statement so we know what the faulting address is in SE mode. --HG-- extra : convert_revision : 6eb2b513c339496a0d013b7e914953a0a066c12d
2006-10-20Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
2006-10-20Use PacketPtr everywhereNathan Binkert
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
and call it packet_access.hh and fix the #includes so things compile right. --HG-- extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-18Zeroed out the actual LSB in addition to moving it's original value the MSB.Gabe Black
--HG-- extra : convert_revision : d29efe01781d72ee6e61818e7b93972262c0616b
2006-10-18Fixed a compiler error, disassembly output, and corrected the address ↵Gabe Black
calculation. --HG-- extra : convert_revision : d34b3c0443064addb6f454ac70fbaeda0678e329
2006-10-18Fixed up ldblockf_p, implemented stdfa properly, and got rid of some old code.Gabe Black
--HG-- extra : convert_revision : 263b4b835d6d1bc9049acdc1398286277bede97a
2006-10-16Corrected the "Authors" lineGabe Black
--HG-- extra : convert_revision : 0202e130b170dcc2f45403c58cf51ec8c2e4e094
2006-10-16Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : 898976bbd322e55bc234035456df8090c6dcf72d
2006-10-16Fix up microcode support.Gabe Black
src/arch/sparc/isa/formats/blockmem.isa: Several small and medium bug fixes. src/cpu/simple/base.cc: Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug. src/cpu/thread_state.cc: Made sure the microPC and nextMicroPC are initialized properly. --HG-- extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
2006-10-16Changed how floating point register numbers are decoded to fit with the spec.Gabe Black
--HG-- extra : convert_revision : 155f48c84d06619c9c1c43375beb9d0a1c7495c9
2006-10-16Made sure the constructor for insts use ExtMachInst rather than MachInst, ↵Gabe Black
since otherwise the EXT_ASI field is lost. src/arch/sparc/isa/base.isa: src/arch/sparc/isa/formats/micro.isa: Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions. src/arch/sparc/utility.hh: Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used. --HG-- extra : convert_revision : cc4363dfe7da81969959cec9d5ad48528edeb8ce
2006-10-15Added an execute function to the macro op so it can be instantiated.Gabe Black
--HG-- extra : convert_revision : 89dd46f5bbac966e6eb4f6f747419fa1d344eb87
2006-10-15Fix how additional template parameters are handled. Non string parameters ↵Gabe Black
are not processed as code. src/arch/isa_parser.py: Changed the way the extra template parameters are specified. MIPS might need to be adjusted. src/arch/sparc/isa/decoder.isa: Changed how Frd_N was set up. src/arch/sparc/isa/formats/blockmem.isa: Fixed up handling of block memory operations src/arch/sparc/isa/formats/integerop.isa: src/arch/sparc/isa/formats/mem.isa: src/arch/sparc/isa/formats/priv.isa: Fix up extra template parameters. --HG-- extra : convert_revision : ebf850d192193521bb84ca36b577051f74338d23
2006-10-13fix a bug in CopyStringOut. dprintk appears to work again.Ali Saidi
--HG-- extra : convert_revision : cd0d13a85ddc7599308db8604a8f63a48679cc05
2006-10-12Changed the sign extension function from mine to the provided one. Mine ↵Gabe Black
relied on implementation specific behavior, namely right shifting a signed value. --HG-- extra : convert_revision : 4f5ef44d012de87919ad681024fe2ed0213a412f
2006-10-12Some support for handling block loads and stores and ASIs properly.Gabe Black
src/arch/sparc/isa/bitfields.isa: Added a field to retrieve the asi from the ExtMachInst src/arch/sparc/isa/decoder.isa: Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field. src/arch/sparc/isa/formats.isa: add includes for the new formats. src/arch/sparc/isa/formats/basic.isa: Add a template for BasicDecodeWithMnemonic which is needed by the unimp format. src/arch/sparc/isa/formats/mem.isa: Change around the memory format to figure out the memory access width on its own. src/arch/sparc/isa/operands.isa: Added support for the operands of block loads/stores which are offset from Frd. src/arch/sparc/utility.hh: Encoded the ASI into the ExtMachInst --HG-- extra : convert_revision : 5c6026a07e3a919e738d27f78beb0faf6b060643
2006-10-12The beginnings of an instruction format to deal with block loads and stores. ↵Gabe Black
This takes advantage of microcode. --HG-- extra : convert_revision : ac912df76c781f40fc462f314451148c5cdfaf43
2006-10-12Some support for macro/micro instructions in SPARC.Gabe Black
--HG-- extra : convert_revision : 1f0687d58ab3a4823911a67d8d5c66b27cc211a5
2006-10-12Support for returning unimplemented instruction in the decoder, lifted from ↵Gabe Black
Alpha --HG-- extra : convert_revision : 7e26053696b23fbc0b8cd5827a5072dcf2526e2b
2006-10-12Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. --HG-- extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-10-06there are two main thrusts of this changeset.Lisa Hsu
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again). 2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier. src/arch/alpha/isa/decoder.isa: src/mem/cache/cache_impl.hh: modify arg. order for new calling convention of exitSimLoop. src/cpu/base.cc: src/sim/main.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args. src/sim/sim_events.cc: src/sim/sim_events.hh: src/sim/sim_exit.hh: add the periodicity of checkpointing back into the code. to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future. --HG-- extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
2006-10-05remove traces of binningNathan Binkert
--HG-- extra : convert_revision : b33cc67cfde04c9af6f50cbef538104e1298bedc
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