| Age | Commit message (Expand) | Author |
|---|
| 2016-11-30 | riscv: [Patch 7/5] Corrected LRSC semantics | Alec Roelke |
| 2016-11-30 | riscv: [Patch 6/5] Improve Linux emulation for RISC-V | Alec Roelke |
| 2016-11-30 | riscv: [Patch 5/5] Added missing support for timing CPU models | Alec Roelke |
| 2016-11-30 | riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A | Alec Roelke |
| 2016-11-30 | riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD | Alec Roelke |
| 2016-11-30 | riscv: [Patch 2/5] Added RISC-V multiply extension RV64M | Alec Roelke |
| 2016-11-30 | arch: [Patch 1/5] Added RISC-V base instruction set RV64I | Alec Roelke |
| 2016-11-21 | x86: fix issue with casting in Cvtf2i | Tony Gutierrez |
| 2016-11-19 | x86: fix loading/storing of Float80 types | Tony Gutierrez |
| 2016-11-17 | alpha: Remove ALPHA tru64 support and associated tests | Andreas Hansson |
| 2016-10-26 | hsail,gpu-compute: fixes to appease clang++ | Tony Gutierrez |
| 2016-10-26 | dev: Add m5 op to toggle synchronization for dist-gem5. | Michael LeBeane |
| 2016-10-26 | gpu-compute: support in-order data delivery in GM pipe | Tony Gutierrez |
| 2016-10-26 | gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex() | Tony Gutierrez |
| 2016-10-26 | gpu-compute, hsail: make the PC a byte address, not an instruction index | Tony Gutierrez |
| 2016-10-26 | gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF | Tony Gutierrez |
| 2016-10-26 | gpu-compute, hsail: call discardFetch() from the WF | Tony Gutierrez |
| 2016-10-26 | hsail, gpu-compute: remove doGm/SmReturn add completeAcc | Tony Gutierrez |
| 2016-10-26 | gpu-compute: remove inst enums and use bit flag for attributes | Tony Gutierrez |
| 2016-10-26 | gpu-compute: move disassemle() implementation to GPUStaticInst | Tony Gutierrez |
| 2016-10-26 | gpu-compute, arch: add some methods to the base inst classes for ISA support | Tony Gutierrez |
| 2016-10-15 | cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass | Fernando Endo |
| 2016-10-13 | isa,arm: Add missing AArch32 FP instructions | Mitch Hayenga |
| 2016-10-04 | kvm: Adding details to kvm page fault in x86 | Alexandru Dutu |
| 2016-09-16 | hsail: Fix disassembly of load instruction with 3 destination operands | Alexandru Dutu |
| 2016-09-16 | gpu-compute: Refactoring Wavefront::dynWaveId | Alexandru Dutu |
| 2016-09-16 | gpu-compute: Wavefront refactoring | Alexandru Dutu |
| 2016-09-15 | arm: Add m5_fail support for aarch64 | Ricardo Alves |
| 2016-09-13 | x86: Force strict ordering for memory mapped m5ops | Michael LeBeane |
| 2016-08-15 | cpu, arch: fix the type used for the request flags | Nikos Nikoleris |
| 2016-08-05 | sim: fix issues with pwrite(); don't enable fstatfs | Tony Gutierrez |
| 2016-08-04 | x86, sim: add some syscalls to X86 | Tony Gutierrez |
| 2016-08-02 | arm: refactor page table walking | Curtis Dunham |
| 2016-08-02 | arm: warn not fail on use of missing miscreg CNTHCTL_EL2 | Dylan Johnson |
| 2016-08-02 | arm: Check TLB stage 2 permissions in AArch64 | Dylan Johnson |
| 2016-08-02 | arm: correctly assign faulting IPA's to HPFAR_EL2 | Dylan Johnson |
| 2016-08-02 | arm: Add TLBI instruction for stage 2 IPA's | Dylan Johnson |
| 2016-08-02 | arm: Fix stage 2 memory attribute checking in AArch64 | Dylan Johnson |
| 2016-08-02 | arm: Fix trapping to Hypervisor during MSR/MRS read/write | Dylan Johnson |
| 2016-08-02 | arm: Fix secure state checking in various places | Dylan Johnson |
| 2016-08-02 | arm: Fix stage 2 determination in table walker | Dylan Johnson |
| 2016-08-02 | arm: Refactor aarch64 table walk logic to remove redundancy | Dylan Johnson |
| 2016-08-02 | arm: Add check to fault routing for hypervisor/virtualization | Dylan Johnson |
| 2016-08-02 | arm: Fix EL perceived at TLB for address translation instructions | Dylan Johnson |
| 2016-08-02 | arm: Add AArch64 hypervisor call instruction 'hvc' | Dylan Johnson |
| 2016-08-02 | arm: add stage2 translation support | Dylan Johnson |
| 2016-08-02 | arm: enable EL2 support | Curtis Dunham |
| 2016-08-02 | arm: invalidate TLB miscreg cache on modification of HSCTLR | Dylan Johnson |
| 2016-08-02 | arm: change instruction classes to catch hyp traps | Dylan Johnson |
| 2016-07-21 | isa: Modify get/check interrupt routines | Mitch Hayenga |
