| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-06-02 | ARM: Add a base class for 32 bit thumb data processing immediate instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add a function to decode 32 bit thumb immediate values. | Gabe Black | |
| 2010-06-02 | ARM: Expand the decoding for 32 bit thumb data processing immediate ↵ | Gabe Black | |
| instructions. | |||
| 2010-06-02 | ARM: Stub out the 32 bit Thumb portion of the decoder. | Gabe Black | |
| 2010-06-02 | ARM: Add bitfields for 32 bit thumb. | Gabe Black | |
| 2010-06-02 | ARM: Decode VFP instructions. | Gabe Black | |
| 2010-06-02 | ARM: Stub out the 16 bit thumb decoder. | Gabe Black | |
| 2010-06-02 | ARM: Add thumb bitfields to the ExtMachInst and the isa definition. | Gabe Black | |
| 2010-06-02 | ARM: Make the decoder handle thumb instructions separately. | Gabe Black | |
| --HG-- rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa | |||
| 2010-06-02 | ARM: Add a thumb bit bitfield. | Gabe Black | |
| 2010-06-02 | ARM: Make the predecoder handle Thumb instructions. | Gabe Black | |
| 2010-06-02 | ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. | Gabe Black | |
| 2010-06-02 | ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst. | Gabe Black | |
| 2010-06-02 | ARM: Add a bit to the ExtMachInst to select thumb mode. | Gabe Black | |
| 2010-06-02 | ARM: Allow ARM processes to start in Thumb mode. | Gabe Black | |
| 2010-06-02 | ARM: Add a new base class for instructions that can do an interworking branch. | Gabe Black | |
| 2010-06-02 | ARM: Track the current ISA mode using the PC. | Gabe Black | |
| 2010-06-02 | ARM: Fix custom writer/reader code for non indexed operands. | Gabe Black | |
| 2010-06-02 | ARM: Remove IsControl from operands that don't imply control transfers. | Gabe Black | |
| Also remove IsInteger from CondCodes. | |||
| 2010-05-25 | x86: put back code that I accidentally deleted | Nathan Binkert | |
| 2010-05-23 | copyright: Change HP copyright on x86 code to be more friendly | Nathan Binkert | |
| 2010-05-14 | SPARC: Implement the version of movcc that uses the fp condition codes. | Gabe Black | |
| 2010-05-12 | X86: Make the cvti2f microop sign extend its integer source correctly. | Gabe Black | |
| The code was using the wrong bit as the sign bit. Other similar bits of code seem to be correct. | |||
| 2010-05-12 | X86: Actual change that fixes div. How did that happen? | Gabe Black | |
| 2010-05-03 | X86: Update the base aux vector X86 processes install. | Gabe Black | |
| 2010-05-02 | X86: Sometimes CPUID depends on ecx, so pass that in. | Gabe Black | |
| 2010-05-02 | X86: Finally fix a division corner case. | Gabe Black | |
| When doing an unsigned 64 bit division with a divisor that has its most significant bit set, the division code would spill a bit off of the end of a uint64_t trying to shift the dividend into position. This change adds code that handles that case specially by purposefully letting it spill and then going ahead assuming there was a 65th one bit. | |||
| 2010-04-15 | tick: rename Clock namespace to SimClock | Nathan Binkert | |
| 2010-03-23 | cpu: fix exec tracing memory corruption bug | Steve Reinhardt | |
| Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes. | |||
| 2010-03-10 | scons: import ply to work around scons sys.path weirdness | Nathan Binkert | |
| 2010-02-26 | cpu_models: get rid of cpu_models.py and move the stuff into SCons | Nathan Binkert | |
| 2010-02-26 | isa_parser: Make SCons import the isa_parser | Nathan Binkert | |
| this is instead of forking a new interpreter | |||
| 2010-02-26 | isa_parser: move the operand map stuff into the ISAParser class. | Nathan Binkert | |
| 2010-02-26 | isa_parser: move more support functions into the ISAParser class | Nathan Binkert | |
| 2010-02-26 | isa_parser: move more stuff into the ISAParser class | Nathan Binkert | |
| 2010-02-26 | isa_parser: move the formatMap and exportContext into the ISAParser class | Nathan Binkert | |
| 2010-02-26 | isa_parser: Make stack objects class members instead of globals | Nathan Binkert | |
| 2010-02-26 | isa_parser: add a debug variable that changes how errors are reported. | Nathan Binkert | |
| This allows us to get tracebacks in certain cases where they're more useful than our error message. | |||
| 2010-02-26 | isa_parser: Use an exception to flag error | Nathan Binkert | |
| This allows the error to propagate more easily | |||
| 2010-02-26 | isa_parser: Move more stuff into the ISAParser class | Nathan Binkert | |
| 2010-02-26 | isa_parser: move code around to prepare for putting more stuff in the class | Nathan Binkert | |
| 2010-02-26 | isa_parser: simple fixes, formatting and style | Nathan Binkert | |
| 2010-02-12 | O3PCU: Split loads and stores that cross cache line boundaries. | Timothy M. Jones | |
| When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them. | |||
| 2010-02-12 | Power ISA: Add an alignment fault to Power ISA and check alignment in TLB. | Timothy M. Jones | |
| 2009-11-05 | compile: compile on 32 bit hardware | Nathan Binkert | |
| 2009-11-05 | isa_parser: allow negative integer literals | Nathan Binkert | |
| 2010-01-19 | util: do checkpoint aggregation more cleanly, fix last changeset. | Lisa Hsu | |
| 1) Move alpha-specific code out of page_table.cc:serialize(). 2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up. 3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN. 4) Fix the memory unserialize that I forgot somehow in the last changeset. 5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py. Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA. | |||
| 2009-12-31 | MIPS: Beef up process initialization. | Matt DeVuyst | |
| 2009-12-31 | MIPS: Implement the SE mode version of rdhwr. | Gabe Black | |
| 2009-12-31 | MIPS: Fix decoding of the rdhwr instruction. | Gabe Black | |
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |