gem5 - gem5

Age	Commit message (Collapse)	Author
2010-08-23	X86: Make the TLB fault instead of panic when something is unmapped in SE mode.	Gabe Black
	The fault object, if invoked, would then panic. This is a bit less direct, but it means speculative execution won't panic the simulator.
2010-08-23	X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.	Gabe Black
	--HG-- rename : src/arch/x86/types.hh => src/arch/x86/types.cc
2010-08-23	X86: Define a noop ExtMachInst.	Gabe Black

2010-08-23	X86: Mark serializing macroops and regular instructions as such.	Gabe Black

2010-08-23	X86: Add a .serializing directive that makes a macroop serializing.	Gabe Black
	This directive really just tells the macroop to set IsSerializing and IsSerializeAfter on its final microop.
2010-08-23	X86: Consolidate extra microop flags into one parameter.	Gabe Black
	This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor.
2010-08-23	ARM: Improve printing of uop disassembly.	Min Kyu Jeong

2010-08-23	ARM: Clean up flattening for SPSR adding	Min Kyu Jeong

2010-08-23	ARM: Implement DBG instruction that doesn't do much for now.	Gene Wu

2010-08-23	MEM: Make CLREX a first class request operation and clear locks in caches ↵	Gene Wu
	when it in received
2010-08-23	ARM: Make sure that software prefetch instructions can't change the state of ↵	Gene Wu
	the TLB
2010-08-23	ARM: Don't write tracedata on writes, it might have been freed already.	Gene Wu

2010-08-23	ARM: Implement CLREX init/complete acc methods	Gene Wu

2010-08-23	ARM: Fix Uncachable TLB requests and decoding of xn bit	Gene Wu

2010-08-23	ARM: For non-cachable accesses set the UNCACHABLE flag	Gene Wu

2010-08-23	ARM: Implement DSB, DMB, ISB	Gene Wu

2010-08-23	ARM: Get SCTLR TE bit from reset SCTLR	Gene Wu

2010-08-23	ARM: Implement CLREX	Gene Wu

2010-08-23	ARM: BX instruction can be contitional if last instruction in a IT block	Gene Wu
	Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond.
2010-08-23	ARM: mark msr/mrs instructions as SerializeBefore/After	Min Kyu Jeong
	Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR
2010-08-23	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.	Min Kyu Jeong
	THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
2010-08-23	ARM: adding genMachineCheckFault() stub for ARM that doesn't panic	Min Kyu Jeong

2010-08-23	ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵	Gene Wu
	ARMv7
2010-08-23	ARM: Temporary local variables can't conflict with isa parser operands.	Gene Wu
	PC is an operand, so we can't have a temp called PC
2010-08-23	ARM: Exclusive accesses must be double word aligned	Ali Saidi

2010-08-23	ARM: Add some registers for big loads/stores to support neon.	Ali Saidi

2010-08-23	ARM: Decode neon memory instructions.	Ali Saidi

2010-08-23	ARM: Clean up the ISA desc portion of the ARM memory instructions.	Gabe Black

2010-08-23	ARM: We don't currently support ThumbEE exceptions, so don't report that we do	Ali Saidi

2010-08-23	ARM: Add system for ARM/Linux and bootstrapping	Ali Saidi

2010-08-23	ARM: Implement some more misc registers	Ali Saidi

2010-08-23	ARM: Fix an un-initialized variable bug	Ali Saidi

2010-08-23	Loader: Make the load address mask be a parameter of the system rather than ↵	Ali Saidi
	a constant. This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0.
2010-08-23	ARM: Finish the timing translation when taking a fault.	Min Kyu Jeong

2010-08-23	ARM: Use a stl queue for the table walker state	Dam Sunwoo

2010-08-23	Compiler: Fixes for GCC 4.5.	Ali Saidi

2010-08-22	X86: Get rid of unused file arguments.hh.	Gabe Black

2010-08-22	SPARC: Fix some style issues in utility.hh.	Gabe Black

2010-08-22	X86: Get rid of the unused getAllocator on the python base microop class.	Gabe Black
	This function is always overridden, and doesn't actually have the right signature.
2010-08-17	x86: minor checkpointing bug fixes	Steve Reinhardt

2010-08-17	sim: revamp unserialization procedure	Steve Reinhardt
	Replace direct call to unserialize() on each SimObject with a pair of calls for better control over initialization in both ckpt and non-ckpt cases. If restoring from a checkpoint, loadState(ckpt) is called on each SimObject. The default implementation simply calls unserialize() if there is a corresponding checkpoint section, so we get backward compatibility for existing objects. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found. (Note that the default warning for a missing checkpoint section is now gone.) If not restoring from a checkpoint, we call the new initState() method on each SimObject instead. This provides a hook for state initializations that are only required when not restoring from a checkpoint. Given this new framework, do some cleanup of LiveProcess subclasses and X86System, which were (in some cases) emulating initState() behavior in startup via a local flag or (in other cases) erroneously doing initializations in startup() that clobbered state loaded earlier by unserialize().
2010-08-13	CPU: Tidy up endianness handling for mmapped "IPR"s.	Gabe Black

2010-07-22	Power: The condition register should be set or cleared upon a system call	Timothy M. Jones
	return to indicate success or failure.
2010-07-22	Power: Provide a utility function to copy registers from one thread context	Timothy M. Jones
	to another in the Power ISA.
2010-07-21	Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses	Tushar Krishna

2010-07-15	ARM: Make an SRS instruction with a bad mode cause an undefined instruction ↵	Gabe Black
	fault.
2010-07-13	ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index.	Gabe Black

2010-06-25	X86: Fix div2 flag calculation.	Gabe Black

2010-06-15	stats: only consider a formula initialized if there is a formula	Nathan Binkert

2010-06-14	stats: get rid of the never-really-used event stuff	Nathan Binkert