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2018-11-05arch, arm: Effect of AT instructions on descriptor handlingAnouk Van Laer
Some address translation instructions will stop translation after the 1st stage and intercept the IPA, even in the presence of stage 2 (eg AT S1E1). However, in the case of a TLB miss, the table descriptors still need to be translated from IPA to PA to avoid fetching the wrong addresses. This commit splits whether IPA->PA translation is required for the VA and/or for the table descriptors. Change-Id: Ie53cdc00585f116150256f1d833460931b3bfb7d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13781 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-29syscall_emul: implement arm openatCiro Santilli
This is especially important because the Ubuntu 18.04 packaged arm-linux-gnueabihf-gcc uses the system call on the program initialization, which leads all programs to fail with: fatal: syscall openat (#322) unimplemented. Change-Id: I5596162ad19644df7b6d21f2a46acc07030001ae Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13004 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-29arch-arm: FIXUP for the add PRFM PST instruction commitYuetsu Kodama
Change-Id: I898e5b565c6591f88ae732b24713aeae2c827cbd Reviewed-on: https://gem5-review.googlesource.com/c/13815 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: We add PRFM PST instruction for armyuetsu.kodama
Note current PRFM supports only PLD, but PST (prefetch for store) is also important for latency hiding. We also bug fix in disassembler to display prfop correctly. Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13 Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp> Reviewed-on: https://gem5-review.googlesource.com/c/13675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}Giacomo Travaglini
According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or 15) is implementation defined; this makes it trappable by having HCR_EL2.TIDCP = 1. Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13780 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPLGiacomo Travaglini
While there is a AArch32 class for instructions accessing implementation defined registers, we are lacking for the AArch64 counterpart. we were relying on FailUnimplemented, which is untrappable at EL2 (except for HCR_EL2.TGE) since it is just raising Undefined Instruction. Change-Id: I923cb914658ca958af031612cf005159707b0b4f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13779 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Refactor AArch64 MSR/MRS trappingGiacomo Travaglini
This patch refactors AArch64 MSR/MRS trapping, by moving the trapping helpers in arch/arm/utility and in the isa code into a MiscRegOp64 class. This class is the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. The common denominator or those instruction is the chance that the system register access is trapped to an upper Exception level. MiscRegOp64 is providing that feature. What do we gain? Other "pseudo" instructions, like access to implementation defined registers can inherit from this class to make use of the trapping functionalities even if there is no data movement between GPRs and system register. Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13778 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Trap to EL2 only if not in Secure StateGiacomo Travaglini
MRS/MSR Instructions should trap to EL2 only if we are in non-Secure state since at the current implementation (Armv8.0) there is no Secure EL2. Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13777 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Fix HVC trapping beahviourGiacomo Travaglini
This patch is fixing HVC trapping behaviour, reusing the pseudocode implementation provided in the arm arm. Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13776 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1Giacomo Travaglini
According to the arm arm, CPTR_EL3.TCPAC traps EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR, are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC. Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13775 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-19arm: treat aarch64 hints as NOPs instead of panicCiro Santilli
Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13476 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-19arm: update hint instruction decoding to match ARMv8.5Ciro Santilli
This fixes: - unallocated hints that have since been allocated - unallocated and unimplemented hint instructions being treated as Unknown instead of the correct NOP - missing encoding for DBG on A32 Unallocated and unimplemented hints give a warning if executed. The most important fix was for the CSDB Spectre mitigation instruction, which was added recently and previously unallocated and treated as Unknown. The Linux kernel v4.18 ARMv7 uses CSDB it and boot would fail with "undefined instruction" since Linux commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13475 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-18null: Stop specifying an endianness in isa_traits.hh.Gabe Black
The NULL ISA doesn't really have an endianness. Now that the packet accessors which consumed that endianness are gone, we can get rid of that setting as well. Change-Id: I8dd4c7b8236b07df4458fea377865f30141121d4 Reviewed-on: https://gem5-review.googlesource.com/c/13466 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-17arch: Include some additional headers in arch/generic/mmapped_ipr.cc.Gabe Black
These had been included transitively before. Change-Id: Ie420bc957e9abb5cd01fcf720fc1fda619d210f0 Reviewed-on: https://gem5-review.googlesource.com/c/13538 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17arch: Get rid of the unused type AnyReg.Gabe Black
This type is defined for all the ISAs but isn't used by anything. Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8 Reviewed-on: https://gem5-review.googlesource.com/c/13539 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12arch: Explicitly specify the endianness in the generic mem helpers.Gabe Black
This avoids using the accessors which automatically assume an endianness, requiring the memory system to know what the guest ISA is. Change-Id: I863fa4116f00e77b801a2f8ea2fbe34e7f55fd5f Reviewed-on: https://gem5-review.googlesource.com/c/13461 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12mips: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: I6220a543686b1d45d26973391b028dc04ce85dd2 Reviewed-on: https://gem5-review.googlesource.com/c/13460 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12sparc: Use big endian packet accessors.Gabe Black
We know data is big endian, so we can use those accessors explicitly. Change-Id: I06fe35254433b20db05f5f10d0ca29a44d47c301 Reviewed-on: https://gem5-review.googlesource.com/c/13458 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12x86: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: I09aa7f1e525ad1346e932ce4a772b64bf59dc350 Reviewed-on: https://gem5-review.googlesource.com/c/13456 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12syscall_emul: update arm uname release to 3.7.0+Ciro Santilli
Trying to compile an ARM C hello world with arm-linux-gnueabihf-gcc from Ubuntu 16.04 leads to a runtime failure with se.py: FATAL: kernel too old because the glibc tests if the kernel is at least 3.2.0, and gem5 was reporting 3.0.0. Furthermore, it is hard to obtain such toolchain at all: for example crosstool-NG currently only allows for minimum kernels above 3.2.0. 3.7.0+ was chosen to match the aarch64 value, as it is likely that the level of support will be very similar. This commit does not guarantee that full 3.7.0 is supported, but it is not likely that we had full 3.0.0 support previously either. However, it is more likely that such support will be eventually achieved if users can at least try out their programs and implement the missing system calls as they are found. Change-Id: I8df3763ae49788a6cb11cb0920e8202cd56b0f09 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12986 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: Add have_crypto System parameterGiacomo Travaglini
This patch adds the have_crypto ArmSystem parameter for enabling crypto extension. This is done by modifying the AArch32/AArch64 ID registers at startup time. Change-Id: I6eefb7e6f6354802a14ea639ad53b75f8e1e11c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13252 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-09arch-arm: AArch64 Crypto AESGiacomo Travaglini
This patch implements the AArch64 AES instructions from the Crypto extension. Change-Id: I9143041ec7e1c6a50dcad3f72d7d1b55d6f2d402 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13250 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch64 Crypto SHAGiacomo Travaglini
This patch implements the AArch64 secure hashing instructions from the Crypto extension. Change-Id: I2cdfa81b994637c880f2523fe37cdc6596d05cb1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13249 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch32 Crypto AESMatt Horsnell
This patch implements the AArch32 AES instructions from the Crypto extension. Change-Id: I51e6deda748b0c26135bcfe9d0c7128f3af91f3d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Matt Horsnell <matt.horsnell@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13248 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch32 Crypto SHAMatt Horsnell
This patch implements the AArch32 secure hashing instructions from the Crypto extension. Change-Id: Iaba8424ab71800228a9aff039d93f5c35ee7d8e5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13247 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
This is an old platform, and we haven't had official Linux kernel configs for it in a while, so we've decided to deprecate it. Furthermore, trying to use it fails with: object 'RealViewEB' has no attribute 'pci_host' and the last commit in the class happened two years ago, which indicates that no one has been using it. Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12471 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-08arch-arm: Mark ArmProcess method as overrideMatteo Andreozzi
Allows compilation on clang3.5+ by fixing Winconsistent-missing-override Change-Id: Ic0ebf3869fc2d9a29fcf7cf5a6535952f41714d0 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13227 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-02sim-se: Set ArmProcess64 hwcaps depending on ID regsGiacomo Travaglini
ArmProcess64 needs to query AArch64 ID registers to check which hw capability is going to report in the appropriate aux vector's entry. Change-Id: I1e1294b831e902226f9b162f25e841e53b940454 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13164 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-02sim-se: Different HWCAP for ArmProcess32/64Giacomo Travaglini
AArch32 and AArch64 have different HWCAP flags in Linux, but we are currently using AArch32 HWCAP flags to initialize the aux vector of both AArch32 and AArch64 binaries. This patch also fixes a bug that was introduced by running in SE mode a target binary compiled with glibc > 2.18. Using AArch32 flags resulted on CPUID flag being set for AArch64. This incorrectly tells libc that emulation of the midr_el1 is supported. In FullSystem this might work, but since we are in Syscall Emulation there is no OS behind emulating the mrs midr_el1 instruction. By separating AArch32 flags from AArch64 flags we are turning off the CPUID hwcap flag in SE mode. Change-Id: I9f651957ba9d19dc2bc06606de070c6586f0f9fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12884 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-02arch-arm: Add FP16 support introduced by Armv8.2-AEdmund Grimley Evans
This changeset adds support for FP/SIMD instructions with half-precision floating-point operands. Change-Id: I4957f111c9c5e5d6a3747fe9d169d394d642fee8 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13084 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-02arch: Fix unserialization of VectorReg valueGabor Dozsa
Change-Id: Iba01ae60e10703877eae299ba924fa1f04a4a387 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13104 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-02arch-arm: Add FP16 support and other primitives to fplibEdmund Grimley Evans
This changeset: - extends fplib to support emulation of half-precision floating-point (FP16) operations; - extends fplib to support additional primitives introduced by the Arm Scalable Vector Extension (SVE) (fplibExpa, fplibScale, fplibTrigMAdd, fplibTrigSMul, fplibTrigSSel); - adds the FZ16 bit to FPSCR; - cleans up fplib code by replacing constants with preprocessor macros and by adding inline functions to recognise NaNs and infinities. Change-Id: If8fdb2a5824b478c8310bbc126ec60cc1105f135 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13044 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Implement AArch64 ID regs as bitunionsGiacomo Travaglini
This patch is implementing the following AArch64 ID registers as bitunions, so that it is easier to query for feature availability: - ID_AA64DFR0_EL1 - ID_AA64ISAR0_EL1 - ID_AA64ISAR1_EL1 - ID_AA64MMFR1_EL1 - ID_AA64MMFR2_EL1 - ID_AA64PFR0_EL1 They are updated to the latest Armv8.5 arch release version. RES0 only ID registers like ID_AA64AFR1_EL1 haven't been added. Change-Id: Ied037abe3757421bcfc2834d397a8cf9a2b9f0a7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13067 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 registerGiacomo Travaglini
This patch implements AArch64 Memory Model Feature Register 2 (from ARMv8.2) Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13066 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Move MiscReg BitUnions into a separate header fileGiacomo Travaglini
As the number of MiscRegs increases there is the need of a cleaner header file; this patch is separating miscreg.[cc,hh] where the miscreg decoding/utility functions are defined/declared from the MiscReg register types (BitUnion). Change-Id: I815f53b117b50e47f93aa13d78356ef09d2a2541 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13065 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Init AArch64 ID registers in SE modeGiacomo Travaglini
One of the auxv vector's flag is the HWCAP, whose bits match the content of several arm ID registers. This patch factors out AArch64 ID registers init into a separate method and creates the symmetric AArch32 ID register init as well, so that we get a meaningful auxiliary vector in SE mode. Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13064 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-28arch-arm: raise/clear IRQ when writing to PMOVSCLR/SETGiacomo Travaglini
Writing a 1 to the Overflow Flag Status register should trigger an interrupt raise/clear depending on the register we are currently using (PMOVSCLR for clearing and PMOVSSET for raising). Change-Id: I2091456685a245712045cf7a4932ac36b7dded1d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12531 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-19syscall_emul: implement dir-related syscallsBrandon Potter
Add getdents, rmdir, chdir, and mknod to SE mode for x86. Change-Id: I387ea3066869e8999bc0064f74070f4e47c1e9a1 Reviewed-on: https://gem5-review.googlesource.com/12112 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
The AuxVector class is responsible for holding Process data. The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9 Reviewed-on: https://gem5-review.googlesource.com/12109 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-13Fix SConstruct for asan buildEarl Ou
Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes some build error when using --with-asan. Bug: None Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7 Reviewed-on: https://gem5-review.googlesource.com/12511 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-13arch-arm: Correction for address size in EL1&0 translationAnouk Van Laer
When doing EL0/1 translation in stage2, the physical address size will be defined by the hypervisor (via VTCR_EL2.ps, not TCR.ips). See D10.2.121 of the ARM ARM. Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12552 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-13arch-arm: Correction to address size in EL2/EL3Anouk Van Laer
This commit corrects how the address size is determined in EL2/EL3. Previously, TCR_ELx.ips was used but this should be TCR_ELx.ps. Change-Id: I7e5a2f376335532a1d1c8c74d12a416617474ae2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12551 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-12dev-arm: rename Pl390 to GicV2Ciro Santilli
The Pl390 model has evolved and acquired a lot of the features from GICv2, which means that the name is no longer appropriate. Rename it to GICv2 since this is more representative of the supported features. GICv2 is backwards compatible with the older Pl390, so we decided to simply rename the class to represent both GICv2 and older interfaces such as the instead of creating a new separate one. Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12492 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10dev-arm: Factory SimObject for generating ArmInterruptPinGiacomo Travaglini
With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10arm: Use the interrupt adaptor in the PMUAndreas Sandberg
Rewrite interrupt handling in the PMU model to use the new interrupt adaptor. Change-Id: I2cbb99580c46d3e21a1335b897843b7b6e41f10c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12400 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-10arm: Add support for tracking TCs in ISA devicesAndreas Sandberg
ISA devices typically need to keep track of the thread context they are associated with. Among other things, this is required for interrupt delivery. Add a BaseISADevice:setThreadContext() method to wire such models to the right thread context. Change-Id: Iad354d176c0c4c4e34c6ab8b5acaee0b69da0406 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12399 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-08-21misc: Appease GCC 8Jason Lowe-Power
GCC 8 adds a number of new warnings to -Wall which generate errors. - Fix memset to 0 for structs by adding casts. - Fix cast with const when the const was ignored. - Fix catch a polymorphic type by value We now compile with GCC 8! Change-Id: Iab70ce11190eee67608fc25c0bedff170152b153 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11949 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2018-08-10arm: Add support for RCpc load-acquire instructions (ARMv8.3)Giacomo Gabrielli
Please note that at the moment these instructions behave like the existing load-acquire instructions, which follow the more conservative RCsc consistency model. This means that the new instructions are _functionally_ correct, but the potential performance improvements enabled by the RCpc model will not be experienced in timing simulations. Change-Id: I04c786ad2941072bf28feba7d2ec6e142c8b74cb Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11989 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-08-02arch-arm: Don't fail to initialise PMU if BP is missingAndreas Sandberg
The branch predictor currently assumes that each CPU has a branch predictor. This isn't true in some cases (e.g., KVM, Atomic). Change-Id: I61e80dca940c2dadba1b812449691c9dba1c06d9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11520 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-07-28arch-riscv: Add xret instructionsAlec Roelke
This patch adds the uret, sret, and mret instructions for use with returning from user-, supervisor-, and machine-level code, respectively. These instructions read the STATUS register to determine the previous privilege level and modify it to re-enable interrupts at the old privilege level. These instructions can only be executed at the corresponding privilege level or higher. Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 Reviewed-on: https://gem5-review.googlesource.com/11136 Maintainer: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de>
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