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AgeCommit message (Expand)Author
2018-10-26arch-arm: Refactor AArch64 MSR/MRS trappingGiacomo Travaglini
2018-10-26arch-arm: Trap to EL2 only if not in Secure StateGiacomo Travaglini
2018-10-26arch-arm: Fix HVC trapping beahviourGiacomo Travaglini
2018-10-26arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1Giacomo Travaglini
2018-10-19arm: treat aarch64 hints as NOPs instead of panicCiro Santilli
2018-10-19arm: update hint instruction decoding to match ARMv8.5Ciro Santilli
2018-10-18null: Stop specifying an endianness in isa_traits.hh.Gabe Black
2018-10-17arch: Include some additional headers in arch/generic/mmapped_ipr.cc.Gabe Black
2018-10-17arch: Get rid of the unused type AnyReg.Gabe Black
2018-10-12arch: Explicitly specify the endianness in the generic mem helpers.Gabe Black
2018-10-12mips: Use little endian packet accessors.Gabe Black
2018-10-12sparc: Use big endian packet accessors.Gabe Black
2018-10-12x86: Use little endian packet accessors.Gabe Black
2018-10-12syscall_emul: update arm uname release to 3.7.0+Ciro Santilli
2018-10-09arch-arm: Add have_crypto System parameterGiacomo Travaglini
2018-10-09arch-arm: AArch64 Crypto AESGiacomo Travaglini
2018-10-09arch-arm: AArch64 Crypto SHAGiacomo Travaglini
2018-10-09arch-arm: AArch32 Crypto AESMatt Horsnell
2018-10-09arch-arm: AArch32 Crypto SHAMatt Horsnell
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
2018-10-08arch-arm: Mark ArmProcess method as overrideMatteo Andreozzi
2018-10-02sim-se: Set ArmProcess64 hwcaps depending on ID regsGiacomo Travaglini
2018-10-02sim-se: Different HWCAP for ArmProcess32/64Giacomo Travaglini
2018-10-02arch-arm: Add FP16 support introduced by Armv8.2-AEdmund Grimley Evans
2018-10-02arch: Fix unserialization of VectorReg valueGabor Dozsa
2018-10-02arch-arm: Add FP16 support and other primitives to fplibEdmund Grimley Evans
2018-10-01arch-arm: Implement AArch64 ID regs as bitunionsGiacomo Travaglini
2018-10-01arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 registerGiacomo Travaglini
2018-10-01arch-arm: Move MiscReg BitUnions into a separate header fileGiacomo Travaglini
2018-10-01arch-arm: Init AArch64 ID registers in SE modeGiacomo Travaglini
2018-09-28arch-arm: raise/clear IRQ when writing to PMOVSCLR/SETGiacomo Travaglini
2018-09-19syscall_emul: implement dir-related syscallsBrandon Potter
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
2018-09-13Fix SConstruct for asan buildEarl Ou
2018-09-13arch-arm: Correction for address size in EL1&0 translationAnouk Van Laer
2018-09-13arch-arm: Correction to address size in EL2/EL3Anouk Van Laer
2018-09-12dev-arm: rename Pl390 to GicV2Ciro Santilli
2018-09-10dev-arm: Factory SimObject for generating ArmInterruptPinGiacomo Travaglini
2018-09-10arm: Use the interrupt adaptor in the PMUAndreas Sandberg
2018-09-10arm: Add support for tracking TCs in ISA devicesAndreas Sandberg
2018-08-21misc: Appease GCC 8Jason Lowe-Power
2018-08-10arm: Add support for RCpc load-acquire instructions (ARMv8.3)Giacomo Gabrielli
2018-08-02arch-arm: Don't fail to initialise PMU if BP is missingAndreas Sandberg
2018-07-28arch-riscv: Add xret instructionsAlec Roelke
2018-07-28arch-riscv: Add support for trap value registerAlec Roelke
2018-07-28arch-riscv: Add support for fault handlingAlec Roelke
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
2018-07-16arch-arm: Introduce RAS System RegistersGiacomo Travaglini
2018-07-09arch-riscv: enable rudimentary fs simulationRobert
2018-07-09arch-riscv: Fix the srlw and srliw instructions.Austin Harris
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