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AgeCommit message (Expand)Author
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
2011-08-19ARM: Fix a memory leak with the table walker.Ali Saidi
2011-08-13X86: Use IsSquashAfter if an instruction could affect fetch translation.Gabe Black
2011-07-15ARM: Fix SWP/SWPB undefined instruction behaviorWade Walker
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
2011-07-11X86: implements copyRegs() functionNilay Vaish
2011-07-11ISA: Get rid of the unused mem_acc_type template parameter.Gabe Black
2011-07-07alpha:hwrei:rollback for o3Korey Sewell
2011-07-05grammar: better encapsulation of a grammar and parsingNathan Binkert
2011-07-05ISAs: Streamline some spots where Mem is used in the ISA descriptions.Gabe Black
2011-07-05ISA parser: Define operand types with a ctype directly.Gabe Black
2011-07-05ISA parser: Simplify operand type handling.Gabe Black
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
2011-07-02ISA: Use readBytes/writeBytes for all instruction level memory operations.Gabe Black
2011-07-02X86: Fix store microops so they don't drop faults in timing mode.Gabe Black
2011-06-28arch: print next upc correctlyNilay Vaish
2011-06-22mips: fix nmsub and nmadd definitionsDeyaun Guo
2011-06-21X86: Eliminate an unused argument for building store microops.Gabe Black
2011-06-19mips: mark unaligned access flag as trueKorey Sewell
2011-06-19inorder/dtb: make sure DTB translate correct addressKorey Sewell
2011-06-19alpha: fix warn_once for prefetchesKorey Sewell
2011-06-19alpha: naming for dtb faultsKorey Sewell
2011-06-19alpha: make hwrei a control instKorey Sewell
2011-06-19sparc: init. cache state in TLBKorey Sewell
2011-06-19cpus/isa: add a != operator for pcstateKorey Sewell
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-06-16ARM: Handle case where new TLB size is different from previous TLB size.Ali Saidi
2011-06-16ARM: Fix memset on TLB flush and initializationChander Sudanthi
2011-06-10sparc: don't use directcntrl branch flagKorey Sewell
2011-06-09sparc: compilation fixes for inorderKorey Sewell
2011-06-07ISA parser: Loosen the regular expressions matching filenames.Gabe Black
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-06-02copyright: clean up copyright blocksNathan Binkert
2011-05-23syscall emul: fix Power Linux mmap constant, plus other cleanupSteve Reinhardt
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
2011-05-23O3: Fix issue with interrupts/faults occuring in the middle of a macro-opGeoffrey Blake
2011-05-18gcc: fix an uninitialized variable warning from G++ 4.5Nathan Binkert
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-13Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.Chander Sudanthi
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
2011-05-06X86: Fix the Lldt instructions so they load the ldtr and not the tr.Gabe Black
2011-05-04ARM: Add support for loading the a bootloader and configuring parameters for itAli Saidi
2011-05-04ARM: Implement WFE/WFI/SEV semantics.Prakash Ramrakhyani
2011-05-04ARM: Add support for MP misc regs and broadcast flushes.Ali Saidi
2011-05-04ARM: Add vfpv3 support to native trace.Ali Saidi
2011-05-04ARM: Fix small bug with vcvt instructionAli Saidi