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This patch moves static portions of the memory instructions out of the
ISA generated code and puts them into arch/riscv/insts. It also
simplifies the definitions of load and store instructions by giving
them a common base class.
Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
Reviewed-on: https://gem5-review.googlesource.com/6024
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts. Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.
Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Reviewed-on: https://gem5-review.googlesource.com/6023
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamically-generated content is left behind for each individual
instruction's implementation. Also, BranchOp is removed due to its
similarity with ImmOp and ImmOp and UImmOp are joined into a single
templated class, ImmOp<T>.
Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Reviewed-on: https://gem5-review.googlesource.com/6022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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This patch introduces the ARM pseudocode haveEL function
into gem5.
Change-Id: I0d96070959e8e13773eb7fa9964894ec0ff2cac2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6162
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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We sometimes need to cast the System pointer stored in a
ThreadContext to an ArmSystem pointer to query global
system setting.
Add an assertion to make sure that the cast resulted in a
valid pointer.
Change-Id: Id382d0c1dceefee8f74d070c205c7b43b83ab215
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6161
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch creates an "insts" directory in src/arch/riscv to store
static portions of instruction definitions that aren't part of the code
generated by the ISA description. It serves as a starting point for
future patches to simplify the ISA description.
Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
Reviewed-on: https://gem5-review.googlesource.com/6021
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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Add support for software breakpoints as signalled by the aarch64 brk
instruction. This introduces a new SoftwareBreakpoint fault.
Change-Id: I93646c3298e09d7f7b0983108ba8937c7331297a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5721
Reviewed-by: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
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Since EL2 is not available in secure mode, any HVC call from secure mode
should be treated as undefined. This behaviour was implemented in
aarch32 HVC but not in 64 bit version
Change-Id: Ibaa4d8b1e8fe01d2ba3ef07494c09a4d3e7e87b0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5921
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch adds all system calls present in riscv-gnu-toolchain at
commit hash 65cb174. Many of them do not have implementations in gem5, so
they are just placeholders.
[Remove the variadic macro and replace it with a function that has
default arguments because variadic macros may not be portable across
compilers]
[Remove spaces around default arguments of createSyscall for better
style]
[Switch from using a loose function to using SyscallDesc's new
constructor]
Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9
Reviewed-on: https://gem5-review.googlesource.com/5322
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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Change-Id: I24008c1e2a94ad8dc4cc13739214928eb846a496
Reviewed-on: https://gem5-review.googlesource.com/5483
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change-Id: Ifbeee464e2d7f872e192f065ad3494f52d274596
Reviewed-on: https://gem5-review.googlesource.com/5482
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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These were just raw C++ classes.
Change-Id: Id2101400d885c6938efb6b94f2949722cfbb94ae
Reviewed-on: https://gem5-review.googlesource.com/5481
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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These had been marked as non-speculative so that their execute
functions would only be called if the instruction should really be
executed. Instead, we can return faults which will cause the same
behavior when the instruction is committed and let the instruction
execute as normal.
Change-Id: I39fa5073e93399424144724b99bdc12070e42286
Reviewed-on: https://gem5-review.googlesource.com/5465
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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These are simple classes which don't need to be in the ISA description.
Change-Id: Ia0bb45f50c4da2536855efcb3c17c7780b431332
Reviewed-on: https://gem5-review.googlesource.com/5464
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The only thing the Unknown format does is return an instance of this
class, so there's no reason to have it in the ISA description.
Change-Id: I3f8187b1450a8622a974c030c0cb552b26f6b5f0
Reviewed-on: https://gem5-review.googlesource.com/5463
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The Nop format mostly just made instructions that inherited from the
Nop base class but with different mnemonics, so there doesn't need
to be very much dynamic content.
Change-Id: I1cf5e25ca8372f9b71f56d49756879c7545c9f6c
Reviewed-on: https://gem5-review.googlesource.com/5462
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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These are for the trap and branch instructions.
Change-Id: Idedab6f3e6c6c954c1f8a36dae52976cf25ad394
Reviewed-on: https://gem5-review.googlesource.com/5461
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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These classes are just used as base classes for other instructions
and don't need to be part of the ISA definition. Pull them into
standard C++ files.
Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554
Reviewed-on: https://gem5-review.googlesource.com/5422
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change the definition of PMU events in order to integrate events not
cannot easily be represented by probe points. The software
increment event is now defined as a special type with its separate
implementation in pmu.cc and pmu.hh.
Change-Id: I43874b9641bf38c54f6ba2c26386542b6a73e282
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5764
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I09531e9992e045254e5ee989dd11ccabbf84e4ce
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5763
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name
Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5862
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name
Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Events were not being attached to counters after a checkpoint resume.
By not storing the enable private variable from the stored state the
recreation of the event to counter association is automatically carried.
The enable state is stored in the reg_pmcnten.
Change-Id: I46344df0882a9050c900efb2e8996d64dbfbf297
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Also, do some minor refactoring to use a BitUnion to pull apart
condition codes, etc.
Change-Id: I0c88878b07a731d0c0fe30f264f53dd795db99ae
Reviewed-on: https://gem5-review.googlesource.com/5421
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Recent Linux kernels for AArch64 have changed their start addresses
but we still want to relocate the kernel to 0x80080000 which
required hacking the load_addr_mask in Realview.py to be 0x7ffffff
from 0xfffffff to mask off the proper number of MSBs to load the
kernel in the desired location. To avoid having to make this change
in the future again, we auto-calculate the load_addr_mask if it is
specified as 0x0 in the System sim-object to find the most restrictive
address mask instead of having the configuration specify it. If the
configuration does specify the address mask, we use it instead of
auto-calculating.
Change-Id: I18aabb5d09945c6e3e3819c9c8036ea24b6c35cf
Signed-off-by: Geoffrey Blake <Geoffrey.Blake@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2323
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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When ignoring writes to the Dummy ISA device (DummyISADevice),
additionally print the value being ignored in the diagnostic.
Sometimes it is useful to know exactly what we are dropping ...
Change-Id: I9a01623611f0da0aa12b065fbb2031aa27e2c036
Signed-off-by: Sean McGoogan <Sean.McGoogan@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5731
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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DSB Instruction shouldn't flush the pipeline, hence the IsSquashAfter
attribute will be removed for either the 32 and 64 bit version.
Change-Id: I98b2b8bc78aa28445ed1a9b5f34645f8d71616ad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5363
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register
shouldn't flush the pipeline as a result of the operation. This addition
was wrongly introduced for supporting self-modifying code. Software
barriers should be used instead.
Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5362
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This Patch is removing the FlushPipe ArmFault, which was used for
flushing the pipeline in favour of the general IsSquashAfter StaticInstr
flag. Using a fault was preventing tracers from tracing barriers like
ISB and from adding them to the instruction count
Change-Id: I176e9254eca904694f2f611eb486c55e50ec61ff
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5361
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32
Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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ARMv8 Tracers might want to be able to read the intWidth field of the
ArmStaticInst object. The field is specifying the bit width of the
integer registers used by the current instruction.
Change-Id: Iaee3123823a2c7380917001c453377c1c12e54a7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5661
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch corrects the encoding of the HVC (Hypervisor Call) for the
T32 instruction set.
Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5541
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Ica08e93f3873a7eafd02fe7d44c3bdbf0ce7f6b7
Reviewed-on: https://gem5-review.googlesource.com/5565
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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A program running in EL0 is allowed to execute CMOs when the UCI bit
in SCTLR is set. The execution of dc ivac, however, would fault
uncoditionally when executed from EL0. This change aligns the
permission checks for dc ivac with the rest of the CMOs.
Change-Id: I1a532f37707c7dc0748b4375252c6ec0bbf95419
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5058
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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In the ISA instruction definitions, some classes were declared with
execute, etc., functions outside of the main template because they
had CPU specific signatures and would need to be duplicated with
each CPU plugged into them. Now that the instructions always just
use an ExecContext, there's no reason for those templates to be
separate. This change folds those templates together.
Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa
Reviewed-on: https://gem5-review.googlesource.com/5401
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.
Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.
Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When decoding VEX prefixed instructions, the x86 predecoder wasn't walking
past the opcode byte and so was also interpreting it as the modRM byte.
Reported-by: likunxi@fas.harvard.edu
Change-Id: I6d4bdabfa03411704c48d905c50c7b23072fc615
Reviewed-on: https://gem5-review.googlesource.com/5281
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The high speed bit-reversing function is now used
for the Aarch64/32 RBIT instruction implementation.
Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5262
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Generating dependency/build product information in the isa parser breaks scons
idea of how a build is supposed to work. Arm twisting it into working forced
a lot of false dependencies which slowed down the build.
Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca
Reviewed-on: https://gem5-review.googlesource.com/5081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0
Reviewed-on: https://gem5-review.googlesource.com/4720
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When a store exclusive is executed, whether it is successful or not,
the exclusives monitor is cleared and therefore we need to signal an
event for the PE.
Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4480
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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ARM systems require the coordination of the global and local
monitors. When the system is run without caches the global monitor is
implemented in the abstract memory object. This change adds a callback
from the abstract memory that notifies the local monitor when the
global monitor is cleared.
Additionally, for ARM systems the local monitor signals the event
register and wakes the thread context up. Subsequent wait-for-event
(WFE) instructions will be immediately signaled.
Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3760
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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MOV Rd,Cd is MR encoded but the control register is operand 2
not operand 1 hence this needs to be MODRM_REG not MODRM_RM.
While MOV Cd,Rd is RM encoded registers are also swapped, so
it also needs to be MODRM_REG as well (as it already correctly is).
This fixes incorrect UD2 reportings leading to invalid traps
reported in O3 on X86 FS introduced with 4e939a7 .
Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8
Reviewed-on: https://gem5-review.googlesource.com/4861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Make the traceData panic for Vectors a warn_once. It's a pity it's
not implemented but it's not a reason to abort the simulation entirely.
Change-Id: I5e97258fd4e3fa385cfe0c4b400524d1f7b154df
Reviewed-on: https://gem5-review.googlesource.com/4860
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The primary difference between loadState and unserialize, at least when
eventually using the default SimObject implementation of loadState, is that
unserialize is called only if there's a corresponding section in the
checkpoint being restored. In this particular case, the AlphaProcess class
calls the generic Process unserialize function, and that does other critical
initialization like set up the processes page table. If the unserialize
function isn't called, other serious problems would break the simulation
anyway.
This removes the final custom implementation of loadState.
Change-Id: If50062392196bd37efd5ba04fd7aee6907b00dc6
Reviewed-on: https://gem5-review.googlesource.com/4741
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The MuxingKvmGic class defined a few functions related to checkpointing which
did nothing other than call the underlying Pl390 implementation. These are
unnecessary in general, and are particularly unnecessary for the loadState
function which is a very lightly used part of the checkpointing interface.
It's not actually defined in Pl390 either, and falls through to the
underlying implementation.
Change-Id: I84aae13d4966df0f4fdd1a72aee0bf1af01392ff
Reviewed-on: https://gem5-review.googlesource.com/4760
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This stat is only incremented by Alpha. Also move the _hwrei into the Alpha
stats object since it's the class that actually sets up and maintains that
value and it probably should have been there all along.
Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0
Reviewed-on: https://gem5-review.googlesource.com/4601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The kernel stat mechanism should really be refactored and moved somewhere
else, but in the mean time there's some old cruft that can be cleared away.
Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86
Reviewed-on: https://gem5-review.googlesource.com/4600
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).
Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4284
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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