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A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.
Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7922
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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A new identifier has been introduced: NUM_PHYS_MISCREGS, which is used
as a boundary for the number of physical (real) Misc registers in the
system. Pseudo registers (like CP15_UNIMPL) have been moved after the
NUM_PHYS_MISCREGS identifier, so that their enum number is
(NUM_PHYS_MISCREGS < number < NUM_MISCREGS). Moving away those
registers has created some free slots that can be used for future Misc
register implementation.
SERIALIZE and UNSERIALIZE now only save/restore PHYSICAL Misc Registers.
This allows us to define as many pseudo registers as we want without
being concerned about checkpoint compatibility.
Change-Id: I7e297b814eeaa4bee640e81bee625fb66710af45
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7921
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The patch fixes one syntax error in TLB::getResultTe
Change-Id: I31a72a52d5c03f43929a69ca1be61d9c20e76f5b
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7983
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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{Load, Store}Double64 didn't consider some of the big-endian
situations. Added big-endian related data conversions to correct them.
Change-Id: I8840613f94446e6042276779d1f02350ab57987f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8145
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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do{Long,L1,L2}Descriptor was not able to load descriptors correctly
for big-endian situations, causing recognised Descriptors. Added
big-endian related data conversions to correct them.
Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8144
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Add an option to automatically set the aarch64 reset vector to the
entry point of the kernel. This is useful when running bare metal
workloads that don't use a normal boot loader.
Change-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8143
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Changing casting type in src/arch/arm/isa.cc
Change-Id: Ia19b30a1bf8b1b25df149b52613a3533eaced03a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8241
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The brk instruction in aarch64 was decoded as an unimplemented
instruction. Fix that.
Change-Id: I3eb36a016ab56d882426c5cdef3a0b594de0f9cd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8142
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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The old code does secure state check by using "el <= EL2", which
mis-considers secure EL1 and EL0. This patch fixes this by using
inSecureState as in ARM ARM.
Change-Id: I01d847c6af022c1462b16206cbc576f15f5569fd
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8081
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The stats are silently non-copy constructible. Therefore, when someone
copy-constructs any object with stats, asserts happen when registering
the stats, as they were not constructed in the intended way.
This patch solves that by explicitly deleting the copy constructor,
trading an obscure run-time assert for a compile-time somehow more
meaningful error meassage.
This triggers some compilation errors as the FaultStats in the fault
definitions of ARM and SPARC use brace-enclosed initialisations in which
one of the elements derives from DataWrap, which is not
copy-constructible anymore. To fix that, this patch also adds a
constructor for the FaultVals in both ISAs.
Change-Id: I340e203b9386609b32c66e3b8918a015afe415a4
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8082
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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A System object has a _numContexts member variable which represent the
number of ThreadContext registered in the System. Since this has to
match the size of the ThreadContext vector, this patch removes the
manually cached size. This was usually used as a for-loop index, whereas
we want to enforce the use of range-based loops whenever possible.
Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8062
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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This patch replaces the dummy values which were defined for the
SecureMonitorTrap thus enabling its usage in aarch32 mode. 1) It
changes the vector table offset from 0x14 to 0x4 in compliance with the
armv8 documentation. 2) When trapping in monitor mode for aarch32, the
mon_lr is updated with the pc + a non zero offset (+4/2 depending on the
current instruction set: +4 for A32, +2 for T32).
Change-Id: I01e1e52bf5ecd405e7472e31e01cf9a599153b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8041
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The old code chose vector offset associated with exceptions taken
to EL3 by incorrectly using "from64", which is associated with the
exception level where the exception was taken from. However, the
offset should depends on the ISA of the lower EL and not of the
starting EL itself, as specified in ARM ARM. This patch corrects
this by implementing the method in AArch64.TakeException in ARM ARM.
Change-Id: I8f7c9aa777c5f2eef9e2d89c36e9daee23f3a822
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8001
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch fixes the Illegal Exception return handler. According to the
armarm documentation, when PSTATE.IL is set to one because of an illegal
exception return, PSTATE.{EL, nRW, SP} are unchanged. This means the
Exception level, Execution state, and stack pointer selection do not
change as a result of the return.
Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8021
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Supervisor Trap is supposed to be able to handle exceptions routed
to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp()
function to Supervisor Trap to handle this, similar to that in
UndefinedFault, DataAbort, etc.
Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7961
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I00f957a3bc4721a66db62b1257f10e9019a94608
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7829
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Change-Id: Ib47f4134e3f0a580e5356d384a5d3b293c1af7be
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7828
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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In AArch32, data cache maintenance instructions that operate by VA do
not generate permission faults.
In AArch64, a data cache invalidate instruction can generate a
permission fault when there are no write permissions to the specified
VA. Data cache clean and data cache clean and invalidate instructions
do not generate permission faults.
Checks for external aborts are also bypassed for data cache
maintenance instructions.
Change-Id: Iea5bc665e4cf66d528e36b671535b66637c4b224
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7827
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The Arm ARM defines that at EL1 a data cache invalidate instruction
performs a data cache clean and invalidate operation if all of the
following apply:
* EL2 is implemented,
* HCR_EL2.VM is set to 1,
* SCR_EL3.NS is set to 1 or EL3 is not implemented.
This changeset implements this behavior.
Change-Id: I6b6aef2f4b1e7eb107c069fdb0a10f4aa8e6b196
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7826
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I2322c7bf65b38cb07a1ea2b5dc25dfc5a0496cf0
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7825
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Cache maintenance operations operate on whole cache blocks. This
changeset uses the system cache line size as the size of the cache
maintenance requests and masks the lower bits of the effective
address.
Change-Id: I6e7aefff51670c8cac39e4e73db21a0c5a0b7aef
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7824
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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A previous change enabled execution of dc ivac from EL0 when
SCTLR_EL1.UCI=1. The Arm ARM specifies that dc ivac is the only data
cache maintenance operation by VA that cannot be executed from
EL0. This changeset essential reverts the change:
8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1
Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7823
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.
Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7982
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch fixes AArch32 SETEND instruction, which was previously
executed unconditionally without checking (H)SCTLR.SED field. This bit
enables/disables the trapping of the instruction.
Change-Id: Ib3d2194c8d16c34ec2a9ab3e8090081900c1e42e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7981
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Fixed Illegal Exception Return detection, which was not
covering all the documented cases.
Change-Id: If08ddc1490d1c0a1fccee1489d116384770ce0a5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7223
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch implements the ELUsingAArch32K pseudocode, which is returning
true if the provided Exception Level is using A32 ISA, but it is not
panicking (quitting simulation) if the information is unknown (see
documentation).
The panicking is the current behaviour of the ELIs32 utility in gem5.
Change-Id: Iad7b56077d7e0f8ee223b5b9593cb8097f26bb29
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7222
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch introduces the inSecureBelow pseudocode function
defined in the armarm documentation. It also replaces the
inSecureState function call which was improperly used in
ELIs32: we might be in secure state (EL3), but with non-secure
lower ELs (SCR.NS = 1).
Change-Id: I01febcb54392ad4e51e785b4d5153aeb3437c778
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7221
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The state of EL1 wasn't determined correctly when running in secure
mode if virtualisation was enabled. This changset updates the
implementation to match the canonical behavior from the ARM ARM.
Change-Id: I7ed6f5c003617773603f678667aac069d73b6f62
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7141
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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ISB Serializing behaviour is guaranteed by IsSquashAfter,
which is inherently serializing; when instruction is commited,
consecutive instructions are flushed and refetched.
Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5701
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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gem5 won't compile correctly since g++ will throw a warning (error)
that the next case statement below this one is reachable since there is
no 'break' statement.
Signed-off-by: Sujay Phadke
Change-Id: Icab646ee5abcfeb6ba3e690909042927b4003eba
Reviewed-on: https://gem5-review.googlesource.com/7521
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I9f208819b8c1a5c46a77262eb533bb47adb2b905
Reviewed-on: https://gem5-review.googlesource.com/7701
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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If set, the granularity bit indicates that the segment limit of segment
descriptors shall be interpreted as number of 4K blocks rather than
bytes.
The high part (bit 48 to 51) of segment descriptor limits is only 4 bits
wide while the low part (bit 0 to 15) spans 16 bits.
Change-Id: Ie386224ca815275fdb31498fe68310ed9c62cc87
Reviewed-on: https://gem5-review.googlesource.com/7601
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This makes riscv compile with the version of clang(++) I have on my
workstation.
Change-Id: I0478616810fbc8a715fd61323b7e0f73676c8328
Reviewed-on: https://gem5-review.googlesource.com/7643
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Move massive initialization routine to the bottom of miscregs.cc.
Additionally, share register metadata across ISA instances by
making lookUpMiscReg a static member of the ISA and only
initializing it once.
Change-Id: I6d6ab26200c4e781151cc6efd97ce2420e2bf4cc
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6803
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Implement proper handling of RES0/RES1 and RAZ/RAO bitfields.
Change-Id: I344c32c3fb1d142acfb0521ba3590ddd2b1f5360
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6802
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The mappings for sharing a backing store between AArch32
and AArch64 system registers are made clearer using an
initializer object.
Change-Id: I29dcfab2797b4d36b3182342997edffde334a291
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6801
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Implements a high level method for generating a Device Tree node for
an AbstractMemory object.
Change-Id: I544ec642f182f103df26de535fdfaf03b3787a08
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5964
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch adds an extra layer to the pyfdt library such that usage
gets easier and device tree nodes can be specified in less code,
without limiting original usage. Note to not import both the pyfdt
and fdthelper in the same namespace (but generally fdthelper is all
you need, because it supplies the same classes even when they are not
extended in any way)
Also, this patch lays out the primary functionality for generating a
device tree, where every SimObject gets an empty generateDeviceTree
method and ArmSystems loop over their children in an effort to merge
all the nodes. Devices are implemented in other patches.
Change-Id: I4d0a0666827287fe42e18447f19acab4dc80cc49
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5962
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.
Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This header is no longer used.
Change-Id: I8da7f8618d647dd11c581818c13855c4e20d32d2
Reviewed-on: https://gem5-review.googlesource.com/7351
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Rather than store the actual TLB entry that corresponds to a mapping,
we can just store some abstracted information (address, a few flags)
and then let the caller turn that into the appropriate entry. There
could potentially be some small amount of overhead from creating
entries vs. storing them and just installing them, but it's likely
pretty minimal since that only happens on a TLB miss (ideally rare),
and, if it is problematic, there could be some preallocated TLB
entries which are just minimally filled in as necessary.
This has the nice effect of finally making the page tables ISA
agnostic.
Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317
Reviewed-on: https://gem5-review.googlesource.com/7350
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The new version extracts all the x86 specific aspects of the class,
and builds the interface around a variable collection of template
arguments which are classes that represent the different levels of the
page table. The multilevel page table class is now much more ISA
independent.
Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636
Reviewed-on: https://gem5-review.googlesource.com/7347
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Use the system object to allocate physical memory instead of manually
placing certain structures and then forcing the system to start other
allocations after them in physical memory.
Change-Id: Ie18c81645c3b648c64a6d7a649a0e50f7028f344
Reviewed-on: https://gem5-review.googlesource.com/7346
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
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Pass this constant into the page table constructor.
Change-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb
Reviewed-on: https://gem5-review.googlesource.com/7345
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
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Don't get it from a global constant declared in an ISA header file.
Change-Id: Ie19440abdd76500a5e12e6791e6f755ad9e95af3
Reviewed-on: https://gem5-review.googlesource.com/7344
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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This avoids having a copy in the lookup function itself, and the
declaration of a lot of temporary TLB entry pointers in callers. The
gpu TLB seems to have had the most dependence on the original signature
of the lookup function, partially because it was relying on a somewhat
unsafe copy to a TLB entry using a base class pointer type.
Change-Id: I8b1cf494468163deee000002d243541657faf57f
Reviewed-on: https://gem5-review.googlesource.com/7343
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The ARM types.hh file defined an STL style hash structure to operate
on the ExtMachInst, but it referred to the underlying storage type
using internal typedefs in the BitUnion types. To avoid having to do
that, this change adds a hash structure to bitunion.hh which will work
on any BitUnion, and gets rid of the ARM ExtMachInst version.
Change-Id: I7c1c84d61b59061fec98abaaeab6becd06537dee
Reviewed-on: https://gem5-review.googlesource.com/7204
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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They are now oriented around a class which makes it easy to provide
custom setter/getter functions which let you set or read bits in an
arbitrary way.
Future additions may add the ability to add custom bitfield methods,
and index-able bitfields.
Change-Id: Ibd6d4d9e49107490f6dad30a4379a8c93bda9333
Reviewed-on: https://gem5-review.googlesource.com/7201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Fold the GDBListener class into the main BaseRemoteGDB class, move
around a bunch of functions, convert a lot of internal functions to
be private, move some functions into the .cc, make some functions
non-virtual which didn't really need to be overridden.
Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d
Reviewed-on: https://gem5-review.googlesource.com/7422
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.
Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.
Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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