gem5 - gem5

Age	Commit message (Expand)	Author
2010-05-14	SPARC: Implement the version of movcc that uses the fp condition codes.	Gabe Black
2010-05-12	X86: Make the cvti2f microop sign extend its integer source correctly.	Gabe Black
2010-05-12	X86: Actual change that fixes div. How did that happen?	Gabe Black
2010-05-03	X86: Update the base aux vector X86 processes install.	Gabe Black
2010-05-02	X86: Sometimes CPUID depends on ecx, so pass that in.	Gabe Black
2010-05-02	X86: Finally fix a division corner case.	Gabe Black
2010-04-15	tick: rename Clock namespace to SimClock	Nathan Binkert
2010-03-23	cpu: fix exec tracing memory corruption bug	Steve Reinhardt
2010-03-10	scons: import ply to work around scons sys.path weirdness	Nathan Binkert
2010-02-26	cpu_models: get rid of cpu_models.py and move the stuff into SCons	Nathan Binkert
2010-02-26	isa_parser: Make SCons import the isa_parser	Nathan Binkert
2010-02-26	isa_parser: move the operand map stuff into the ISAParser class.	Nathan Binkert
2010-02-26	isa_parser: move more support functions into the ISAParser class	Nathan Binkert
2010-02-26	isa_parser: move more stuff into the ISAParser class	Nathan Binkert
2010-02-26	isa_parser: move the formatMap and exportContext into the ISAParser class	Nathan Binkert
2010-02-26	isa_parser: Make stack objects class members instead of globals	Nathan Binkert
2010-02-26	isa_parser: add a debug variable that changes how errors are reported.	Nathan Binkert
2010-02-26	isa_parser: Use an exception to flag error	Nathan Binkert
2010-02-26	isa_parser: Move more stuff into the ISAParser class	Nathan Binkert
2010-02-26	isa_parser: move code around to prepare for putting more stuff in the class	Nathan Binkert
2010-02-26	isa_parser: simple fixes, formatting and style	Nathan Binkert
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
2010-02-12	Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.	Timothy M. Jones
2009-11-05	compile: compile on 32 bit hardware	Nathan Binkert
2009-11-05	isa_parser: allow negative integer literals	Nathan Binkert
2010-01-19	util: do checkpoint aggregation more cleanly, fix last changeset.	Lisa Hsu
2009-12-31	MIPS: Beef up process initialization.	Matt DeVuyst
2009-12-31	MIPS: Implement the SE mode version of rdhwr.	Gabe Black
2009-12-31	MIPS: Fix decoding of the rdhwr instruction.	Gabe Black
2009-12-31	MIPS: Implement the set_thread_area system call.	Gabe Black
2009-12-31	MIPS: Create an artificial control register to hold the thread pointer.	Gabe Black
2009-12-31	MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.	Gabe Black
2009-12-21	MIPS: Add missing syscall slots.	Gabe Black
2009-12-20	Alpha: Implement MVI and remaining BWX instructions.	Soumyaroop Roy
2009-12-19	X86: Add a common named flag for signed media operations.	Gabe Black
2009-12-19	X86: Create a common flag with a name to indicate high multiplies.	Gabe Black
2009-12-19	X86: Create a common flag with a name to indicate scalar media instructions.	Gabe Black
2009-11-17	ARM: Begin implementing CP15	Ali Saidi
2009-11-17	ARM: Differentiate between LDM exception return and LDM user regs.	Ali Saidi
2009-11-17	ARM: Boilerplate full-system code.	Ali Saidi
2009-11-16	imported patch isa_fixes2.diff	Ali Saidi
2009-11-15	ARM: Make the exception return form of ldm restore CPSR.	Gabe Black
2009-11-15	ARM: Create a new type of load uop that restores spsr into cpsr.	Gabe Black
2009-11-14	ARM: Check in the actual change from the last commit.	Gabe Black
2009-11-14	ARM: Fix up the implmentation of the msr instruction.	Gabe Black
2009-11-14	ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.	Gabe Black
2009-11-14	ARM: Add a bitfield to indicate if an immediate should be used.	Gabe Black
2009-11-14	ARM: Write some functions to write to the CPSR and SPSR for instructions.	Gabe Black
2009-11-14	ARM: Fix up the implmentation of the mrs instruction.	Gabe Black
2009-11-14	ARM: More accurately describe the effects of using the control operands.	Gabe Black