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2020-01-07arch,sim: Stop decoding the pseudo inst subfunc value.Gabe Black
This isn't used by anything any more. The func field is left in place to ensure compatability, but there's no reason to decode a value nobody is going to use. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I85fcd0e4a362551c29af6bff350d99af86050415 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23179 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2020-01-06arch,sim: Use the guest ABI mechanism with pseudo instructions.Gabe Black
Right now, there are only two places which call the pseudoInst function directly, the ARM KVM CPU and the generic mmapped IPR. These two callers currently use the generic "PseudoInstABI" which is just a wrapper around the existing getArgument function. In the future, this getArgument function will be disolved, and the PseudoInstABI will be defined for each ABI. Since it currently mimics the Linux ABI since gem5 can only handle one ABI at a time right now, this implementation will probably be shared by linux system calls, except that the pseudo inst implementation will eat return values since those are returned through other means when the pseudo inst is based on magic address ranges. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Ied97e4a968795158873e492289a1058c8e4e411b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23178 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06arch-arm: Semihosting, specify files root dirAdrian Herrera
This patch adds an option to "ArmSemihosting" which allows for specifying an optional search path for host files. Previously, behaviour was fixed to search in the directory from where the gem5 binary was run from. Change-Id: I57b932b38d022f132af78857104633d7bfdd1442 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23903 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-30fastmodel: Fix compilation errorsChun-Chen TK Hsu
This changes fixes two compilation errors when compiling with FastModels. One is that CurrentMsn should be Iris::CurrentMsn and the other is that currEL() function needs arch/arm/utility.hh header file. Test by compiling GEM5 with FastModels: scons -j64 build/ARM/gem5.opt \ USE_ARM_FASTMODEL=1 \ PVLIB_HOME=... \ MAXCORE_HOME=... \ ARMLMD_LICENSE_FILE=... \ Change-Id: Iabe0a5f25246591f99b57219428b8f87ecd3363c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23924 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.Gabe Black
Now that the IRIS thread context can be specific to ARM, some things which had been pushed to a different level of abstraction can be mvoed back. This will hopefully allow more code sharing in the future when other types of CPUs are supported. Change-Id: Ic3a5f0db53ebe93e18f7507ed71812bce27b6d01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23788 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-27fastmodel: Move the ARM IRIS threadcontext into CortexA76.Gabe Black
This specialization will correspond specifically with the CortexA76, instead of specializing the ThreadContext for ARM in general. Some aspects of this class may need to move into the base IRIS thread context class, but I'll leave that for a later change. Change-Id: I9cbe527d36e6fda78601dc39c1963370cfa28b16 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23787 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-27fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.Gabe Black
Fast models are in practice only ARM, so it's not that helpful to have the ARM-ness factored out. It is, however, helpful to have aspects which control how gem5 concepts like registers are mapped to fast model concepts like resources, especially since these mappings may vary from fast model to fast model. For instance, it looks like the CortexA76 does not have predicate vector registers. Rather than make all fast models support or not support those registers, that can be done on a model by model basis. Change-Id: I195da4a2f4d2f8593032d0d63e9fd3d20a240d01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23786 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.Gabe Black
The generic thread context checkpointing code can be used which calls into the ThreadContext methods to read the required state. Change-Id: Ib5c318ff4d2e756274b4c90b56533b2689a837f2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23785 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Handle "special" vector regs without calling into IRIS.Gabe Black
These registers don't have an architectural equivalent, but they may need to be accessed by generic code, for instance the code that checkpoints a thread context. Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-24fastmodel: Implement readVecRegFlat for ArmThreadContext.Gabe Black
This just calls readVecReg after constructing a RegId. Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-24fastmodel: Determine what space to use for breakpoints dynamically.Gabe Black
This was hardcoded as 5, but should be determined based on the memory space IDs the fast model returns. What we do now is have a specific override for ARM (perhaps conceptually the A76) which looks for an address space called "Current" which seems to work well. It's possible that the appropriate address space for a different model might have a different number, or even a different name. This may need to be further specialized/parameterized in those cases. Change-Id: Ie1ef99675fd9bccab50b7fc7add16b82a93bd60b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22143 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-23fastmodel: Implement PC based events.Gabe Black
These use the IRIS breakpoint API to stop the models at the appropriate points. There seems to be a slightly wonky interaction between breakpoints and stepping, where if you stop at a breakpoint and then step, you might end up moving forward more than the number of requested instructions. Change-Id: I31f13a120cfc1ad2ec3669ee8befd6d21b328bb2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22122 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-20arch-arm: Fix clang warningsJui-min Lee
Fix some warnings reported by clang. * missing override in {freebsd,linux}/process.hh Change-Id: I67c36a0785ac90614211d640fd58d3ffe187c17e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23863 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-19arch-arm: Fix decoding of LDFF1x scalar plus scalarAdrià Armejach
First-faulting loads do allow Rm == 0x1f. Change-Id: Ib9bcb55e126653813fdbb7c29970af23a2471ebb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23803 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: Semihosting, fix SYS_FLENAdrian Herrera
SYS_FLEN was incorrectly handled as SYS_ISTTY. This patch fixes this behaviour. Change-Id: I66e0b97d8b44d2cb78e0b1bb940fd6f4b52c658f Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23752 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: Secure EL2 checkingAdrian Herrera
This patch adds Armv8.4-SecEL2 checking. Helpers implementing EL2Enabled, IsSecureEL2Enabled and HaveSecureEL2Ext following the architecture pseudocode are provided. These are intended to be used for checking register access permissions. Change-Id: I3d06d0127cf165c1eeaf3302830742d610cef719 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23766 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: AArch64 trap check, arbitrary ECs/ImmsAdrian Herrera
This patch generalises trap checking when accessing system registers in AArch64. Depending on the accessed register, a different Exception Class (EC) and immediate value may be set. Previously this only took SIMD traps into account. Change-Id: I30717676a210c770531e39e4c6a6e1fbfdfdc583 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23765 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18x86: Fix some bugs with KVM in SE mode on Intel machines.Gabe Black
The granularity bit should be set since the segment limit should be interpreted as a number of pages, not bytes. A comment indicates that NX support is enabled, but the bit wasn't being set. That's now set to be consistent with FS mode. The SVME bit is now turned off, since Intel CPUs don't have SVME, and enabling it apparently makes them upset. Also disable CR4 bits which enable features neither gem5 nor apparently my workstation support. Change-Id: I72d5a07871dede8763b0dd188a52fe5eb6bde6ea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23361 Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Tell fast model not to shutdown when time stops.Gabe Black
Change-Id: I000e7809a2c8850eb31e5615caf1d88b537fea8d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22121 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Implement port proxies.Gabe Black
This plumbing is simple and largely copied from other implementations within gem5. This mechanism should be refactored so that the duplication is unnecessary. Change-Id: Ibcdf759b7fba1d574e8e2ba04249afdd92c6560c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22120 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Create a TLB model which uses IRIS to do translations.Gabe Black
Change-Id: I806dc8cdacce57e6ec31d2421b9e6b9733c7da02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22119 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-17fastmodel: Add an address translation mechanism to the ThreadContext.Gabe Black
This will be used by the TLB to do the actual translation. Unfortunately there isn't a great way to tell what translation type to use, so we just go through all of them for now. The ARM subclass might specialize and figure out which address spaces to use based on control register state. Change-Id: Id1fcad66554acf9d69af683917b3c2834f825da0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22118 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Add a header for IRIS MSN constants.Gabe Black
Change-Id: I06a7d7db95ec1ce65945c9e09f812f0b69aaa8e6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23643 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11arch-arm: Always initialize SVE memDataGiacomo Travaglini
Some compilers will produce a warning when using an uninitialized memData. JIRA: https://gem5.atlassian.net/browse/GEM5-196 Change-Id: I19e197b15729a03da546a0188917a9b3e7bf31b7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23525 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11arch-arm: Avoid creating an empty byteEnable vectorGiacomo Travaglini
This behaviour will be forbidden in following patches. Instead, create an all true vector. JIRA: https://gem5.atlassian.net/browse/GEM5-196 Change-Id: I61d2852610281f2d7c7a669dcb4d2728be194f52 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23524 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
The x86 version doesn't do anything x86 specific, and so can be used generically in sim/pseudo_inst.(hh|cc) Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
The logic that determines which syscall to call was built into the implementation of faults/exceptions or even into the instruction decoder, but that logic can depend on what OS is being used, and sometimes even what version, for example 32bit vs. 64bit. This change pushes that logic up into the Process objects since those already handle a lot of the aspects of emulating the guest OS. Instead, the ISA or fault implementations just notify the rest of the system that a nebulous syscall has happened, and that gets propogated upward until the process does something with it. That's very analogous to how a system call would work on a real machine. When a system call happens, the low level component which detects that should call tc->syscall(&fault), where tc is the relevant thread (or execution) context, and fault is a Fault which can ultimately be set by the system call implementation. The TC implementor (probably a CPU) will then have a chance to do whatever it needs to to handle a system call. Currently only O3 does anything special here. That implementor will end up calling the Process's syscall() method. Once in Process::syscall, the process object will use it's contextual knowledge to determine what system call is being requested. It then calls Process::doSyscall with the right syscall number, where doSyscall centralizes the common mechanism for actually retrieving and calling into the system call implementation. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I937ec1ef0576142c2a182ff33ca508d77ad0e7a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23176 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10x86: Stop manually clearing RFLAGS.RF after a system call.Gabe Black
The system call stub KVM uses in SE mode to call the system call pseudo instruction which ultimately calls m5Syscall already uses sysret, and the implementation of sysret clears both the RF and VM bits itself. There's no reason to do that again explicitly here. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Id7b5417564e3f3492ba6efb8ed36fab2f4c38e09 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23175 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
Setting syscall args isn't really something we need to do in gem5, since that will be taken care of by the code actually calling the syscall. We just need to be able to retrieve the value it put there. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I0bb6d5d0207a7892414a722b3788cb70ee509582 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23174 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Stop using setSyscallArg to set argc and argv.Gabe Black
In Alpha and MIPS, the argc and argv values should be in what happens to be the first and second syscall argument registers, but that's not by definition. The process objects of both those ISAs know what registers to use intrinsically, so there's also no reason to call out to a helper method which acts as a part of the Process's interface to the rest of gem5. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Id8fa38ab1fc2ac6436e94ad41303439973fded10 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23173 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I9bbffcc74ec4f3df4effa5c50f0a4a688c5b6016 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23169 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch-arm: Disambuiguate NumFloatV7ArchRegs usageGiacomo Travaglini
Sometimes NumFloatV7ArchRegs is used to specify the maximum number of AArch32 floating point registers. Sometimes it is just used for indexing a free register storage to be used by microcode. In that scenario, VecSpecialElem should be used, which is a index to the first available non architectural register for floating point. Change-Id: I4e84740701f0e7041cf1acad2afed471361c423a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23107 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Unify VLdmStm behaviour when reg out of indexGiacomo Travaglini
The generic VLdmStm class (modelling A32 VLDM/VSTM) is handling a wrong register list in a inconsistent way. Some instructions are opting for being decoded as Unknown, while others handle it inside the macro instruction constructor by manually adjusting the reglist. Those are two valid implementation of the CONSTRAINT UNPREDICTABLE behaviour (1 and 3): "If regs > 16 || (d+regs) > 32 , then one of the following behaviors must occur: 1) The instruction is UNDEFINED . 2) The instruction executes as NOP . 3) One or more of the SIMD and floating-point registers are UNKNOWN . If the instruction specifies writeback, the base register becomes UNKNOWN . This behavior does not affect any general-purpose registers." This patch unfies the behaviour by always opting for option 1) over 3) Change-Id: I4f98409243d5a2ec64113fe9c87e961a391abe94 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23106 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Fix NumVecV7ArchRegs value (64->16)Giacomo Travaglini
In armv7 there are 16 only quadword (vector) registers which are usable by SIMD instructions (Q0-Q15). Those completely overlap with the 32 double word registers (D0-D31). NumVecV7ArchRegs = 16; // Q0-Q15 Change-Id: Id8fee1064d60dcfa54f273fa7d579a20c0087835 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23105 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Reorder arch/arm/registers.hh constantsGiacomo Travaglini
This is putting some order in the constants definition, respecting the description which divides: * Constants Related to the number of registers (example: const int NumFloatRegs = 0) from: * Semantically meaningful register indices (to indicate special registers) (example: const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs) Change-Id: I1760b7f786b6f6becbe8ab445e65fc3fa17206cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23104 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegsGiacomo Travaglini
gem5-ARM is not using floatRegs anymore and moved towards the vecRegs register file (which is used for SIMD&FP + SVE instructions) Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-08arch-riscv: set MaxMiscDestRegs to 2Alec Roelke
In an earlier patch, the FCSR was split into its two components, FRM and FFLAGS, causing explicit writes to FCSR to incur two CSR writes. With the O3 CPU model, which defers them both to later, this creates a bug where an assertion that the number of CSR writes must be less than MaxMiscDestRegs fails because that constant is 1. This patch sets it to 2 so the O3 CPU is compatible with this scheme. Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23220 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-06kvm,arm: Update the KVM ARM v8 CPU to use vector regs.Gabe Black
The exact mapping of the KVM registers and the gem5 registers is direct and may not actually be correct. Change-Id: Idb0981105c002e65755f8dfc315dbb95ea9370df Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23402 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-05arch-x86: missing override specifierAndrea Mondelli
Change-Id: I5a6db4632ec5b670cbfeb7d52190a7545c0b985f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23380 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-05arch-x86: Adding LDDQU instructionmarjanfariborz
Tested with simple c binaries. Signed-off-by: marjanfariborz <mfariborz@ucdavis.edu> Change-Id: I2f0852b136f966381d29af523e8ffdbca795afcd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23262 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sparc: Fix the getresuidFunc prototype.Gabe Black
When the syscall signature was changed to not take a Process pointer, the prototype for getresuidFunc was not updated. Change-Id: I887cc3e3aa8483fc608df9963876a0ac6fa2251d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23320 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sparc: Fix the predecoder's moreBytes method.Gabe Black
Endianness transformation was moved from the CPU into this method, making the "inst" parameter guest endian instead of host endian. The emi member of the decoder was set using the betoh method, ensuring that it was still stored in host order. Unfortunately, the "inst" parameter was used in some places when setting up the rest of emi. This change replaces those uses of inst with emi. Change-Id: I0c7f9a1833db4b64fc1a5015cf10f6ba3f7c26a0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23163 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03fastmodel: Switch the diagnostic pragmas to GCC from clang.Gabe Black
Clang can handle both, and GCC throws a fit if it sees pragmas for clang. Change-Id: Ie9f2789f45706223b11ed5acdf8b371de6e7ee24 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23321 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03systemc,fastmodel: Use the gem5_scons error and warning functions.Gabe Black
Use them in place of messing with termcap directly. Change-Id: I093efa95e6b6ea7af198dc1395dce05ca6d6575f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23263 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03fastmodel: Suppress a spurious warning on clang for amba_pv.h.Gabe Black
This header comes from the fast model distribution and so we can't (easily) disable the warning locally. Change-Id: I2c1eee48f8970bb17466f0759f0077a5d45e76af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23123 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-01arch-riscv: Fix disassembling of immediate for c.lui instructionIan Jiang
For compressed instruction c.lui, the 6-bit immediate is left-shifted by 12 bits in decoding. While the original Gem5 gives the left-shifted value directly in disassembly. This patch fixes the problem by adding a new template CILuiExecute to resume the immediate before outputting it in disassembly. Note: The immediate is sign-extended to 20-bit to be compatible with GCC. Change-Id: If73f72d3e8f85a8b10ce7a323379d8ad6c4c3085 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22567 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28arm: Make sure not to shift off of the end of a uint32_t in KVM.Gabe Black
The methods which set or get an attribute from the virtual GIC use a shift constant which is 32, but they store their result in a 32 bit variable and, according to clang, are used to shift 32 bit inputs. This is undefined behavior in terms of the shift, and will truncate off the value regardless. Change-Id: Ie9543ab9e6e1d5f86317a9210d220928b23ffaf8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23129 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-26arch-arm: Make the Tarmac parsed registers case insensitiveGiacomo Travaglini
This will make parsing more robust, considering the tarmac format changes between AA32 and AA64. Change-Id: I0e4905d70e2e494104706a4c6c75b8169deaecf9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22845 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch-riscv: Fix immediate decoding for integer shift immediate instructionsIan Jiang
The "shamt" in integer shift immediate instructions is an unsigned immediate encoded in bits[25:20]. While the original Gem5 uses bits[31:20] as an int64_t. This patch fixes the problem by: - Adding a new parameter "imm_code" for format IOp and use the correct bitfields SHAMT5 or SHAMT6 to assign "imm_code" for each instruction. - Use uint64_t instead of default int64_t to assign parameter "imm_type" of format IOp. The instructions affected include: - Shift Left Logical Immediate, slli - Shift Right Logical Immediate, srli - Shift Right Arithmetic Immediate, srai - Shift Left Logical Word Immediate, slliw - Shift Right Logical Word Immediate, srliw - Shift Right Arithmetic Word Immediate, sraiw Change-Id: Iad34ccd036c11630409f84f6de2b939224e100e6 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22563 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch-riscv: Fix disassembling for fence and fence.iIan Jiang
The original Gem5 does not give correct disassembly for instruction fence and fence.i. This patch fixes the problem by adding two bitfields PRED and SUCC and a new format FenceOp and a template FenceExecute, in which operands are generated based on PRED and SUCC in the disassembling function. Change-Id: I78dbf125fef86ce40785c498a318ffb1569da46c Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22569 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-06 21:00:52 +0000