gem5 - gem5

Age	Commit message (Expand)	Author
2019-05-17	arch-arm: implement VMINNM and VMAXNM SIMD version	Ciro Santilli
2019-05-17	arch-arm: rename operands to match spec in isa/formats/fp.isa	Ciro Santilli
2019-05-14	arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher	Javier Bueno
2019-05-11	arch-arm: Add initial support for SVE contiguous loads/stores	Giacomo Gabrielli
2019-05-07	x86: Mark translation as delayed in case of a hw page table walk	Gabor Dozsa
2019-05-04	arch-riscv: Implement MHARTID CSR	Alec Roelke
2019-05-03	sim-se: add eventfd system call	Brandon Potter
2019-05-03	arch-riscv,isa: Fix for compressed jump (c_j) imm	Avishai Tvila
2019-04-30	arch: Stop using TheISA within the ISAs.	Gabe Black
2019-04-30	x86: Get rid of some unnecessary TheISA-es in x86.	Gabe Black
2019-04-30	sparc: Move translation constants from isa_traits.hh into tlb.hh.	Gabe Black
2019-04-30	sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.	Gabe Black
2019-04-30	arch: Remove the mt.hh switching header.	Gabe Black
2019-04-30	cpu: alpha: Delete all occurrances of the simPalCheck function.	Gabe Black
2019-04-30	alpha: Implement simPalCheck within the ISA description.	Gabe Black
2019-04-30	cpu: Remove hwrei from the generic interfaces.	Gabe Black
2019-04-30	arch: cpu: Track kernel stats using the base ISA agnostic type.	Gabe Black
2019-04-30	alpha: Implement HWREI in the ISA.	Gabe Black
2019-04-30	alpha: Add some control registers to the ISA operands list.	Gabe Black
2019-04-29	mips: Implement readRegOtherThread and setRegOtherThread directly.	Gabe Black
2019-04-29	arch-arm: Faults DebugFlag now printing inst opcode if available	Giacomo Travaglini
2019-04-29	arch-arm: Report real instruction encoding when Undefined	Giacomo Travaglini
2019-04-28	arch, sim: Simplify the AuxVector type.	Gabe Black
2019-04-28	mem: Remove the ISA specialized versions of port proxy's read/write.	Gabe Black
2019-04-28	mem: Minimize the use of MemObject.	Gabe Black
2019-04-26	arch-arm: updateMiscReg not setting isHyp in aarch64	Giacomo Travaglini
2019-04-26	arm: Factor some repetition out of the ProcessInfo constructor.	Gabe Black
2019-04-25	arm: Fix some style issues in stacktrace.cc.	Gabe Black
2019-04-25	x86: Refactor the ProcessInfo constructor.	Gabe Black
2019-04-25	x86: Fix some style issues in stacktrace.cc.	Gabe Black
2019-04-25	arch-arm: Remove un-needed hyp flag in TLBI operations	Giacomo Travaglini
2019-04-25	arch-arm: Correct target EL field in TLBI operations	Giacomo Travaglini
2019-04-22	sim-se: Enhance clone for X86KvmCPU	Alexandru Dutu
2019-04-22	cpu: Eliminate the ProxyThreadContext class.	Gabe Black
2019-04-11	arch-arm: Enable PMSELR_EL0 read in PMU	Giacomo Travaglini
2019-04-03	misc: Removed inconsistency in O3* debug msgs	Andrea Mondelli
2019-04-02	dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt	Giacomo Travaglini
2019-04-01	dev-arm: Correct cast of template parameter	Andrea Mondelli
2019-03-28	arch-arm: Fix use of bitwise operators on booleans	Javier Setoain
2019-03-28	arch-arm: Fix index generation for VecElem operands	Giacomo Travaglini
2019-03-25	arch-arm: Add missing fall-through defaults	Javier Setoain
2019-03-25	arch-power: Rename program counter registers	Sandipan Das
2019-03-25	arch-power: Simplify doubleword operand types	Sandipan Das
2019-03-22	sim-se: Fixed initialization array size	Tiago Muck
2019-03-21	dev-arm: ambiguous use of getPort()	Andrea Mondelli
2019-03-19	arch, cpu, dev, gpu, mem, sim, python: start using getPort.	Gabe Black
2019-03-14	arch-arm,cpu: Add initial support for Arm SVE	Giacomo Gabrielli
2019-03-11	arch-hsail: changed gen.py shebang from python(3) to python2.7	Ryan Gambord
2019-03-11	arch-arm: Fixing implicit fallthrough build errors	Ryan Gambord
2019-03-01	mem-cache: alias to mem::getMasterPort in TLB class	Andrea Mondelli