gem5 - gem5

Age	Commit message (Expand)	Author
2019-09-06	arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking	Giacomo Travaglini
2019-09-06	arch-arm: Add explicit AArch64 MiscReg banking	Giacomo Travaglini
2019-09-06	arch-arm: Use same template across all MSR inst	Giacomo Travaglini
2019-09-06	arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex	Giacomo Travaglini
2019-09-06	arch-arm: fix GDB stub after SVE	Ciro Santilli
2019-09-06	arch-arm: SGI registers undecoded in AArch32	Giacomo Travaglini
2019-09-06	arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs	Giacomo Travaglini
2019-09-05	arch-x86: Adding warning for movnti	Pouya Fotouhi
2019-09-05	arch-x86: implement movntq/movntdq instructions	Pouya Fotouhi
2019-08-30	arm,kvm: Fix python imports from global namespace	Giacomo Travaglini
2019-08-28	mem: Eliminate the Base(Slave\|Master)Port classes.	Gabe Black
2019-08-23	arch-riscv: fix GDB register cache	Alec Roelke
2019-08-21	arch-riscv: Update register file	Yifei Liu
2019-08-21	arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0	Ciro Santilli
2019-08-21	arch-arm: Fix implicit fallthrough build errors	Chun-Chen TK Hsu
2019-08-20	arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL	Giacomo Travaglini
2019-08-20	arch-arm: Replace direct use cpsr.el with currEL helper	Giacomo Travaglini
2019-08-20	arch-arm: Overload currEL helper with CPSR argument	Giacomo Travaglini
2019-08-20	arch-arm: Rewrite the currEL helper method to use opModeToEL	Giacomo Travaglini
2019-08-16	x86: Stop CPUID from claiming we support xsave.	Gabe Black
2019-08-15	x86: Make unsuccessful CPUID instructions zero the result.	Gabe Black
2019-08-12	arch-arm: Added LD/ST<op> atomic instruction family and SWP instrs	Jordi Vaquero
2019-08-12	arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func	Jordi Vaquero
2019-08-10	x86: Move some fixed or dummy config information into X86LocalApic.py.	Gabe Black
2019-08-09	arch: Bump MaxVecRegLenInBytes to 4096	Tony Gutierrez
2019-08-07	arch-arm: Add TypeAtomicOp class to be used by new atomic instructions	Jordi Vaquero
2019-08-07	arch-arm: adding register control flags enabling LSE implementation	Jordi Vaquero
2019-08-06	sim-se: add new getpgrp system call	Brandon Potter
2019-08-06	sim-se: adding pipe2 syscall	Matthew Sinclair
2019-08-05	arch-arm: Implement ARMv8.1-PAN, Privileged access never	Giacomo Travaglini
2019-08-05	arch-arm: Rewrite MSR immediate instruction class	Giacomo Travaglini
2019-07-27	arch-arm: Fix reg dependency for SVE gather microops	Gabor Dozsa
2019-07-27	arch-arm: Fix tracing code for SVE gather	Gabor Dozsa
2019-07-27	arch-arm: Add SVE LD1RQ[BHWD]	Javier Setoain
2019-07-27	arch-arm: Fix decoding for SVE memory instructions	Adrià Armejach
2019-07-27	arch-arm: Add support for SVE load/store structures	Javier Setoain
2019-07-22	arch-x86: Don't free PTW state with inflight requests	Matthew Poremba
2019-07-19	arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disable	Giacomo Travaglini
2019-07-19	arch-arm: Add HPD bit for TCR_EL2/EL3	Giacomo Travaglini
2019-07-19	arch-arm: Clean Fault generation when processing Long Descriptor	Giacomo Travaglini
2019-07-18	arch-arm: Add first-/non-faulting load instructions	Gabor Dozsa
2019-07-17	arch-arm: Use ExceptionLevel type in TlbEntry	Giacomo Travaglini
2019-07-16	arch-x86: add unconditional tag to calls/returns	Hoa Nguyen
2019-06-26	arch, arm: Update miscRegs in getTE	Anouk Van Laer
2019-06-17	arch-arm: Move the memacc_code before op_wb in fp loads	Giacomo Travaglini
2019-06-10	arch-arm: implement VMINNM scalar thumb	Ciro Santilli
2019-06-07	arch-arm: Fix WalkerState,Descriptors default constructor	Giacomo Travaglini
2019-05-31	x86: fix movsd bug on %xmm register	Brandon Potter
2019-05-31	arm: Fix decoding of CRC32 instructions in thumb32	Chun-Chen TK Hsu
2019-05-31	arch-arm: Treat SVE prefetch instructions as no-ops	Giacomo Gabrielli