summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Expand)Author
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
2019-01-25arch-arm: Remove floatReg operand typeGiacomo Travaglini
2019-01-25arch-arm: Use VecElem instead of FloatReg for FP instructionGiacomo Travaglini
2019-01-25arch: Fix VecElem Operand generation in ISA parserGiacomo Travaglini
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
2019-01-25arch-arm: Inital vector rename mode depending on A32/A64Giacomo Travaglini
2019-01-25arch-arm: Remove unused float operandsGiacomo Travaglini
2019-01-25arch: Provide traceback when parsing ISA codeGiacomo Travaglini
2019-01-24hsail: Remove the MiscReg type.Gabe Black
2019-01-24base: arch: Get rid of the now unused FloatRegVal type.Gabe Black
2019-01-23arch-arm: Implement LoadAcquire/StoreRelease in AArch32Giacomo Travaglini
2019-01-23arch-arm: IsStoreConditional flag set depending on flavorGiacomo Travaglini
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
2019-01-23arm: Replace MiscReg with RegVal in utility.(hh|cc).Gabe Black
2019-01-22sparc: Get rid of some register type definitions.Gabe Black
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-22arm: Get rid of some register type definitions.Gabe Black
2019-01-22arch-arm: implement the GDB XML target description for ARMCiro Santilli
2019-01-22arch-arm: Move AArch32 IMPLEMENTATION DEFINED registersGiacomo Travaglini
2019-01-22sim-se add readv and modifies writevBrandon Potter
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
2019-01-22sim-se: add socket-based functionalityBrandon Potter
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
2019-01-16arm: Make the fp register types 64 bits.Gabe Black
2019-01-16arch-arm: Read VMPIDR instead of MPIDR when EL2 is EnabledGiacomo Travaglini
2019-01-16arch-arm: Added TLBI_ALL EL2 instructionAnouk Van Laer
2019-01-16arch-riscv: Add interrupt handlingAlec Roelke
2019-01-16arch-riscv: Fix reset function and styleAlec Roelke
2019-01-15arch-arm: Fix usage of RegId constructor for VecElemGiacomo Travaglini
2019-01-14arm: Stop using the FloatReg and FloatRegBits types.Gabe Black
2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
2019-01-10arch-arm, sim-se: Add support for TLS in cloneAndreas Sandberg
2019-01-10arch-arm, sim-se: Fix incorrect SP handling in cloneAndreas Sandberg
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
2019-01-10arch-arm, sim-se: Wire up syscalls needed for pthreadsJavier Setoain
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
2019-01-09arch-arm: Additional bits in misc ARM registers to use with the TLB and page ...Ivan Pizarro
2019-01-03arm: properly handle RES0/1 for SCTLRsCurtis Dunham
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
2018-12-19arch-arm: Add Crypto in SE modeGiacomo Travaglini
2018-12-18arch: Make the ISA parser always use binary floating point accessors.Gabe Black
2018-12-05arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.ccTony Gutierrez
2018-12-03arch-arm: correctly set floats from GDB on aarch64Ciro Santilli
2018-12-03arch-arm: only change the pc address when GDB registers are setCiro Santilli
2018-12-03arch-arm: fix the aarch64 GDB stubCiro Santilli
2018-11-28arch-arm: Add missing template declarationNikos Nikoleris
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-09 22:49:22 +0000